System for controlling a clock signal for synchronizing a counter to a received value and method thereof
AssigneeATI Technologies, Inc.
InventorsBranko Kovacevic, Kevork Kechichian
Life of this patent
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Abstract
In accordance with a specific embodiment of the present invention one of a first, second, and third reference signal generator is selected. When a first reference signal generator is selected, a value associated with the pulse width modulated register is compared to a second register to control generation of the reference clock. When a second reference signal generator is selected, a phase accumulator is used to generate the reference clock. When a third reference signal generator is selected, a digital phase locked loop generates the reference clock. The present invention is better understood with reference to specific embodiments.
Claims18
A video processor system comprising:
- a video rendering engine having an input to receive a reference clock;
- a multiplexer having a first input, a second input, a third input, a select input, and an output coupled to the rendering engine input;
- a first reference clock generator having an output coupled to the multiplexer first input, the first reference clock generator including a system time clock counter having an output coupled to an input of a pulse width modulated (PWM) comparator, the PWM comparator having an output to be coupled to a first controlled oscillator to generate the reference clock;
- a second reference clock generator having an output coupled to the multiplexer second input, the second reference clock generator including a phase accumulator having an output to be coupled to a second controlled oscillator to generate the reference clock;
- and
- a third reference clock generator having an output coupled to the multiplexer third input, the third reference clock generator including a digital phase locked loop to generate the reference clock.
A method of processing video, the method comprising:
- selecting one of a first reference signal generator, second reference signal generator, and third reference signal generator;
- generating a reference signal using the first reference signal generator when the first reference signal generator is selected;
- generating the reference signal using the second reference signal generator when the second reference signal generator is selected;
- generating the reference signal using the third reference signal generator when the third reference signal generator is selected;
- and
- using the reference signal to determine when a video image is to be displayed.
A video processor system comprising:
- a video rendering engine having an input to receive a reference clock;
- a multiplexer having a first input, a second input, a select input, and an output coupled to the rendering engine input;
- a first reference clock generator having an output coupled to the multiplexer first input, the first reference clock generator including a system time clock counter having an output to be coupled to a first controlled oscillator to generate the reference clock;
- a second reference clock generator having an output coupled to the multiplexer second input.
A video processor system comprising:
- a video rendering engine having an input to receive a reference signal;
- a first reference module including
- register having a predetermined number of bits;
- an arithmetic module having a first input coupled to the register, a second input, and an output;
- a latch having a first input coupled to at least a first portion of the arithmetic module output, and an output coupled to the second input of the arithmetic module,
- an output node coupled to a second portion of the arithmetic module output, the output node to provide a control signal to an oscillator to generate the reference signal.
A video processor system comprising:
- a video rendering engine having an input to receive a reference signal;
- a first clock node;
- a digital phase locked loop (DPLL) having a first input coupled to the first clock node, a second input, and a first reference clock output, and a second reference clock output;
- a system time clock counter having an increment input coupled to the first reference clock output, and an output;
- a system time clock register;
- a control portion having an first input coupled to the system time clock counter output, a second input coupled to the system time clock register, a third input coupled to second clock reference output, and an output coupled to the DPLL second input.
A method of processing video, the method comprising:
- receiving a first clock;
- generating a first reference clock and a second reference clock using the first clock and a divisor M;
- and
- modifying the divisor M based at least partially on a received Motion Picture Expert Group (MPEG-TYPE) Clock Reference Program (PCR).
Dependencies are inferred from the claim text.