Ensuring video buffer verifer integrity in MPEG-like encoding

A method for use in an encoder to ensure integrity of a hypothetical decoder buffer of a video buffer verifier comprising the steps of:

• supplying a variable video encoding bit rate;
• maintaining a model buffer including a first bit content;
• said model buffer being representative of said hypothetical decoder buffer and said first bit content of said model buffer being representative of an inferred bit content of said hypothetical decoder buffer;
• maintaining an encoder buffer including a second bit content;
• in response to a control signal, controllably inhibiting transmission of bits from said encoder buffere;
• generating said control signal in accordance with a prescribed relationship dependent on said variable video encoding bit rate, said first bit content and said second bit content for generating said control signal;
• generating a representation of a delay interval between encoding a video frame and decoding said video frame;
• in response to said variable video encoding bit rate and said delay interval, generating a representation of a number of bits drained from said encoder buffer during a prescribed interval and in responsive to said instantaneous encoding video rate, said representation of bits drained, said first bit content and said second bit content, generating said control signal;
• said step of generating said representation of bits drained includes a step of employing;
• ∫ t - eeD t ⁢ video_rate ⁢ ( τ ) ⁢ ⁢ ⅆ τ = drainIntegral ,
• where video rate is the instantaneous encoding video bit rate, eeD in said delay interval and drainIntegral is the representation of bits drained.

Apparatus for use in an encoder to ensure integrity of a hypothetical decoder buffer of a video buffer verifier comprising:

• a source of a substantially constant video encoding bit rate;
• an encoder buffer including a second bit content;
• a video encoder having a bit rate controller including a model buffer having a first bit content, said model buffer being representative of said hypothetical decoder buffer and said first bit content of said model buffer being representative of an inferred bit content of said hypothetical decoder buffer, said video encoder having a substantially constant encoding bit rate and generates a representation of a delay interval between encoding a video frame and decoding said video frame;
• a transmission controller responsive to a control signal for controllably inhibiting transmission of bits from said encoder buffer;
• and
• a control signal generator for generating said control signal in accordance with a prescribed relationship dependent on said video encoding bit rate, said first bit content and said second bit content for generating said control signal,
• said control signal generator being responsive to said video substantially constant encoding bit rate, said first bit content, said second bit content and said delay interval to generate said control signal in accordance with said prescribed relationship during prescribed intervals that a predetermined relationship exists between bits drained from said encoder buffer and bits supplied to said encoder buffer,
• said control signal being generated during said prescribed intervals that the number of bits drained from said encoder buffer is greater than the number of bits supplied to said encoder buffer, and
• said prescribed relationship being in accordance with xsBits being incremented by bits_drained−video_rate×T, and said control signal being generated when xsBits>0, wherein T is a prescribed interval, bits_drained is the number of bits drained from said video buffer during interval T, video_rate is the video encoding bit rate, and video_rate×T is the number of bits supplied to said video buffer during interval T.

A method for use in an encoder to ensure integrity of a hypothetical decoder buffer of a video buffer verifier comprising the steps of:

• supplying a substantially constant video encoding bit rate;
• maintaining a model buffer including a first bit content,
• said model buffer being representative of said hypothetical decoder buffer and said first bit content of said model buffer being representative of an inferred bit content of said hypothetical decoder buffer;
• maintaining an encoder buffer including a second bit content;
• in response to a control signal, controllably inhibiting transmission of bits from said encoder buffer;
• generating said control signal in accordance with a prescribed relationship dependent on said variable video encoding bit rate, said first bit content and said second bit content for generating said control signal;
• and
• generating a representation of a delay interval between encoding a video frame and decoding said video frame;
• said step of generating said control signal utilizes said substantially constant video encoding bit rate, said first bit content, said second bit content and said delay interval to generate said control signal in accordance with said prescribed relationship during prescribed intervals that a predetermined relationship exists between bits drained from said encoder buffer and bits supplied to said encoder buffer, and generates said control signal during said prescribed intervals that the number of bits drained from said encoder buffer is greater than the number of bits supplied to said encoder buffer, and
• said prescribed relationship is in accordance with xsBits being incremented by bits_drained−video_rate×T, and said control signal is generated when xsBits>0, wherein T is a prescribed interval, bits_drained is the number of bits drained from said video buffer during interval T, video_rate is the video encoding bit rate, and video_rate×T is the number of bits supplied to said video buffer during interval T.