Data communications circuit with multi-stage multiplexing

A method of multiplexing data onto a communication link comprising:

• multiplexing parallel bits of a lower frequency signal to an intermediate frequency signal of parallel bits using a clock signal distributed from a clock source;
• and
• multiplexing the bits of the intermediate frequency signal to a higher frequency signal on the communication link using the clock signal more precisely distributed from the clock source.

A data multiplexer for multiplexing data onto a communication link comprising:

• low frequency data multiplexer means relying on a clock signal distributed from a clock source for multiplexing parallel bits of a lower frequency signal to an intermediate frequency signal of parallel bits;
• and
• higher frequency data multiplexer means relying on the clock signal more precisely distributed from a clock source for multiplexing the bits of the intermediate frequency signal to a higher frequency signal on the communication link.

A data communication circuit for serializing data on a communication link comprising, on a single electronic chip:

• a higher frequency data multiplexing stage on the chip coupled between the communication link and an intermediate frequency signal, a data stream on the communication link having a first number of one or more bitstreams and the intermediate frequency signal having a data stream of a second number of parallel bits greater than the first number;
• and
• a lower frequency data multiplexing stage on the chip coupled to the higher frequency data multiplexing stage between the intermediate frequency signal and a lower frequency signal, the lower frequency signal having a data stream of a third number of parallel bits greater than the second number.

A data multiplexer on an electronic chip for multiplexing data onto a communication link comprising:

• a lower frequency data multiplexer on the chip which multiplexes parallel bits of a lower frequency signal to an intermediate frequency signal of parallel bits;
• and
• a higher frequency data multiplexer on the chip coupled to the lower frequency data multiplexer which multiplexes the bits of the intermediate frequency signal to a higher frequency signal on the communication link.

A method of multiplexing data on an electronic chip onto a communication link comprising:

• multiplexing on the chip parallel bits of a lower frequency signal to an intermediate frequency signal of parallel bits;
• and
• multiplexing on the chip the bits of the intermediate frequency signal to a higher frequency signal on the communication link.