Switch matrix among tributaries of a telecommunication network and managing method thereof

A method of managing a switch matrix of tributaries of a telecommunication network, specifically a telecommunication network operating on flows of data that are arranged according to SDH protocol, which is divided in a set of parallel branches, each of said branches comprising:

• at least a first space stage carrying out on the input data flow a selection and packing of a subset of data to be exchanged,
• a second time stage storing the subset of data to be exchanged, the write and read operations in a random access memory device of said second time stage being controlled by a write memory and a read memory through write and read words, with said memories being in turn driven by a microprocessor and a master counter, in said second time stage, during updating of the random access memory, said read and write operations being performed simultaneously using spare read memories and spare write memories, wherein the method comprises:
• associating a single spare read memory to read memories on each parallel branch and a single spare write memory to write memories on each parallel branch;
• selecting, via selecting means, either the output of the spare read memory or the output of the read memory, as well as the output of the spare write memory and the write memory;
• writing a write sequence in the spare write memory during the updating of the random access memory;
• checking, during the writing of the read word in the write memory whether the read word written in the read memory, which represents the address to be read in the random access memory, is greater or smaller than the address whereto said read word is written in the read memory itself;
• driving said selecting means to select the spare read memory if the address is greater, or to select the read memory if the address is smaller;
• and
• selecting the read memory definitively at the end of write operation of the read word in said read memory and employ the spare write memory in association with a write memory belonging to another branch.

A method of managing a switch matrix of tributaries of a telecommunication network, specifically a telecommunication network operating on flows of data that are arranged according to SDH protocol, which is divided in a set of parallel branches, each of said branches comprising:

• at least a first space stage carrying out on the input data flow a selection and packing of a subset of data to be exchanged,
• a second time stage storing the subset of data to be exchanged, the write and read operations in a random access memory device of said second time stage being controlled by a write memory and a read memory through write and read words, with said memories being in turn driven by a microprocessor and a master counter, in said second time stage, during updating of the random access memory, said read and write operations being performed simultaneously using spare read memories and spare write memories, wherein the method comprises:
• associating a single spare read memory to read memories on each parallel branch and a single spare write memory to write memories on each parallel branch;
• selecting, by selecting means, either the output of the spare read memory or the output of the read memory, as well as the output of the spare write memory and the write memory;
• writing a write sequence in the spare write memory during the updating of the random access memory;
• selecting the output of the spare write memory supplying the write sequence to both the selecting and packing means and the write memory;
• selecting the output of the write memory, after it has been written with the write sequence, and employ the spare write memory in association with a write memory belonging to another branch;
• providing the first space stage with the write sequence;
• employing said write sequence to obtain control signals to drive a recursive structure of shifter circuits;
• and
• employing said recursive structure of shifter circuits to pack the set of data to be exchanged, wherein the recursive structure of shifter circuits is obtained through a plurality of stages, and in that each shifter circuit, equipped with q inputs, carries out an up shift or down shift on q bits available at its q inputs by a number of locations ranging from 0 to q−1.

A method of managing a switch matrix of tributaries of a telecommunication network, specifically a telecommunication network operating on flows of data that are arranged according to SDH protocol, which is divided in a set of parallel branches, each of said branches comprising:

• at least a first space stage carrying out on the input data flow a selection and packing of a subset of data to be exchanged,
• a second time stage storing the subset of data to be exchanged, the write and read operations in a random access memory device of said second time stage being controlled by a write memory and a read memory through write and read words, with said memories being in turn driven by a microprocessor and a master counter, in said second time stage, during updating of the random access memory, said read and write operations being performed simultaneously using spare read memories and spare write memories, wherein the method comprises:
• associating a single spare read memory to read memories on each parallel branch and a single spare write memory to write memories on each parallel branch;
• selecting, by selecting means, either the output of the spare read memory or the output of the read memory, as well as the output of the spare write memory and the write memory;
• writing a write sequence in the spare write memory during the updating of the random access memory;
• selecting the output of the spare write memory supplying the write sequence to both the selecting and packing means and the write memory;
• selecting the output of the write memory, after it has been written with the write sequence, and employ the spare write memory in association with a write memory belonging to another branch;
• providing the first space stage with the write sequence;
• employing said write sequence to obtain control signals to drive a recursive structure of shifter circuits;
• and
• employing said recursive structure of shifter circuits to pack the set of data to be exchanged, wherein the selecting of the output of the spare read memory or the output of the read memory, as well as the output of the spare write memory and the write memory, is carried out by a recursive structure of adders which execute subsequent sums on the bits forming the write sequence, supplying control signals as intermediate or final results.