US 6,674,686 B2 · Method and apparatus for read operation and write operation in semiconductor memory device

Abstract

Methods and apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus. Read and write operations are sequentially performed in a same cycle using QDR2 (Quadruple Data Rate 2) wherein each of the input and output modes operate at a 2-bit burst mode and a double data rate (DDR) mode, thereby minimizing cycle time or read and write operations are sequentially performed in a same cycle using QDR4 (Quadruple Data Rate 4), wherein each of the input and output modes operate at a 4-bit burst mode and a DDR mode, thereby minimizing the cycle time. In another aspect, when a read command is input in one cycle, a read operation is performed in synchronization with a rising edge of clock and a write operation is performed in synchronization with a signal that operates during the read operation.

Claims28

Dependent claims

A method for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus, the method comprising the steps of:

performing a read operation in synchronization with a clock signal when a read command is input at one cycle;
and
performing a write operation in the one cycle in synchronization with a signal that is generated in response to the read operation.

An apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus, the apparatus comprising:

an address register for latching an a read address or a write address;
a clock buffer for receiving clock signals;
a decoder for decoding a read or write address that is latched by the address register;
a memory cell array for enabling word lines and row paths in response to an address decoding signal received from the decoder;
a sense amplifier that is enabled for a read operation when a word line and a row path are enabled;
a write driver that is enabled for a write operation to write data in a cell when a word line and a row path are enabled;
a data output register for latching output data and outputting the output data in synchronization with a clock in a following cycle after the sense amplifier is enabled;
a data input register;
and
a controller for tracking a random signal that is generated in response to an earlier read or write operation to thereby synchronize a subsequent write or read operation.

7 more elements

Dependencies are inferred from the claim text.

Method and apparatus for read operation and write operation in semiconductor memory device

Life of this patent

Method and apparatus for read operation and write operation in semiconductor memory device

Life of this patent

Abstract

Claims28