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US 6,674,685 B2Granted
Semiconductor memory device having write column select gate
AssigneeRenesas Technology Corp.
InventorTakeshi Fujino
Life of this patent
Estimating the term…
Abstract
A DRAM includes a sense amplifier which is activated when first and second nodes are set respectively to L and H levels to amplify a potential difference between paired bit lines. The DRAM further includes a write column select gate which is activated when the first node is set to L level to write a data signal on a pair of write data lines into a corresponding sense amplifier when a corresponding write column select line is set to H level. In this way, the data signal can be written into the sense amplifier simultaneously with sensing and amplification of memory cell data, which can enhance the random access rate.
Claims10
A semiconductor memory device allowing a data signal to be rewritten thereinto, comprising:
- a memory block including a plurality of memory cells arranged in rows and columns, a plurality of word lines provided correspondingly to said rows respectively, and a plurality of pairs of bit lines provided correspondingly to said columns respectively;
- a sense amplifier provided correspondingly to each pair of bit lines and activated in response to application of a first drive potential to a first node to amplify a potential difference generated between the bit lines of the corresponding bit line pair;
- a row decoder selecting one of said plurality of word lines according to a row address signal to activate each memory cell corresponding to the selected word line;
- a column decoder selecting one of said plurality of pairs of bit lines according to a column address signal;
- a pair of write data lines provided commonly to said plurality of pairs of bit lines;
- a write circuit, according to a write data signal, setting one of first and second write data lines included in said pair of write data lines to a first potential and setting the other of said first and second write data lines to a second potential;
- and
- a write column select gate transmitting, in write operation, the data signal on said pair of write data lines to the pair of bit lines selected by said column decoder,
- said write column select gate including
- first and second transistors provided for each pair of bit lines, having respective gate electrodes connected to said first and second write data lines respectively and having respective first electrodes both connected to said first node, and
- third and fourth transistors provided for each pair of bit lines, having respective first electrodes connected to respective second electrodes of said first and second transistors and having respective second electrodes connected respectively to first and second bit lines of the corresponding pair of bit lines, the third and fourth transistors being rendered conductive, in the write operation, in response to selection of the corresponding pair of bit lines by said column decoder.
8 more elements
A semiconductor memory device allowing a data signal to be rewritten thereinto, comprising:
- a memory block including a plurality of memory cells arranged in rows and columns, a plurality of word lines provided correspondingly to said rows respectively, and a plurality of pairs of bit lines provided correspondingly to said columns respectively;
- a sense amplifier provided correspondingly to each pair of bit lines and activated in response to application of a first drive potential to a first node to amplify a potential difference generated between the bit lines of the corresponding bit line pair;
- a row decoder selecting one of said plurality of word lines according to a row address signal to activate each memory cell corresponding to the selected word line;
- a column decoder selecting one of said plurality of pairs of bit lines according to a column address signal;
- a pair of write data lines provided commonly to said plurality of pairs of bit lines;
- a write circuit, according to a write data signal, setting one of first and second write data lines included in said pair of write data lines to a first potential and setting the other of said first and second write data lines to a second potential;
- and
- a write column select gate transmitting, in write operation, the data signal on said pair of write data lines to the pair of bit lines selected by said column decoder,
- said write column select gate including
- first and second transistors provided in common to each of said plurality of pairs of bit lines, having respective gate electrodes connected to said first and second write data lines respectively and having respective first electrodes both connected to said first node, and
- third and fourth transistors provided for each pair of bit lines, having respective first electrodes connected to respective second electrodes of said first and second transistors and having respective second electrodes connected respectively to first and second bit lines of the corresponding pair of bit lines, the third and fourth transistors being rendered conductive, in the write operation, in response to selection of the corresponding pair of bit lines by said column decoder.
8 more elements
Dependencies are inferred from the claim text.