Multi-bank chip compatible with a controller designed for a lesser number of banks and method of operating
AssigneeInfineon Technologies North America Corp.
InventorWilliam Wu Shen
Life of this patent
Estimating the term…
Abstract
A memory chip and a method of operating a chip with a number of banks of memory to be backward compatible with a controller designed to operate a chip having a lesser number of banks. To accomplish this, a control (bit) is produced on the chip Mode Register Set (MRS) that activates corresponding logic in the chip to move one of the bits used to address a memory cell, such as one of the row address bits, to a position of the bank ID field. This provides a greater number of bank ID bits to select memory banks of a chip so that a high number bank chip can accept a command supplied by a controller designed to operate a chip with a fewer number of banks and that has a format of a lesser number of bank ID bits.
Claims9
A memory chip comprising:
- a plurality of memory banks each containing a plurality of memory cells arranged in rows and columns;
- a mode register circuit responsive to commands from an external controller for producing a mode register set of bank identification bits, row address bits and column address bits to select a memory cell in one of said plurality of memory banks to provide a command function for said selected memory cell;
- and
- an address register receiving said bank identification bits and said row and column address bits and using at least one of said row address bits or said column address bits as an additional bank identification bit to increase the number of memory banks from which selection of one of said plurality of memory banks can be made.
A method for selecting a memory cell in a chip having a plurality of memory banks in each of which a plurality of memory cells are arranged in rows and columns when using an external controller that produces commands to operate a chip having a lesser number of memory banks, comprising the steps of:
- providing from said controller commands to produce a mode register set of bank identification bits corresponding to selection of one of said lesser number of memory banks, row address bits and column address bits;
- and
- using one of said row address bits or column address bits of said mode register set as an added bank identification bit to permit selection of one of said plurality of memory banks.
Dependencies are inferred from the claim text.