US 6,674,683 B2Granted

Serial access memory

AssigneeOki Electric Industry Co., Ltd.

InventorShigemi Yoshioka

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Abstract

A serial access memory low in current consumption, capable of restraining an increase in chip size even if memory capacity increases. The serial access memory has a first and a second memory arrays each having memory cells electrically connected to corresponding bit lines, signal lines provided in common between the memory arrays and electrically connected to the corresponding bit lines through first transfer circuits, write registers electrically connected to the corresponding signal lines through a second transfer circuit, a write bus electrically connected to the write registers through a third transfer circuit, an input circuit electrically connected to the write bus, read registers electrically connected to the corresponding signal lines through a fourth transfer circuit, a read bus electrically connected to the read registers through a fifth transfer circuit, and an input circuit electrically connected to the read bus.

Claims17

Dependent claims

A serial access memory comprising:

a first memory array including a first memory cell and a pair of first bit lines, said first memory cell being selectively coupled to a corresponding bit line of said pair of first bit lines according to a voltage level of a first word line;
a second memory array including a second memory cell and a pair of second bit lines, said second memory cell being selectively coupled to a corresponding bit line of said pair of second bit lines according to a voltage level of a second word line;
a pair of first column lines selectively coupled to said pair of first bit lines or said pair of second bit lines, said pairs of first and second bit lines being located between the first column lines of said pair of first column lines;
a coupling control circuit that provides control to selectively couple said pair of first column lines to said pair of first bit lines or said pair of second bit lines according to first select information;
a first read register selectively coupled to said pair of first column lines;
and
a read control circuit that provides control to selectively couple said first read register to at least one column line of said pair of first column lines according to a second select information.

4 more elements

A serial access memory comprising:

a first memory array including a first memory cell and a pair of first bit lines, said first memory cell being selectively coupled to a corresponding bit line of said pair of first bit lines according to a voltage level of a first word line;
a second memory array including a second memory cell and a pair of second bit lines, said second memory cell being selectively coupled to a corresponding bit line of said pair of second bit lines according to a voltage level of a second word line;
a first column line selectively coupled to a bit line of said pair of first bit lines or a bit line of said pair of second bit lines;
a coupling control circuit that provides control to selectively couple said first column line to the bit line of said pair of first bit lines or the bit line of said pair of second bit lines according to first select information;
a read register selectively coupled to said first column line;
and
a read control circuit that provides control to selectively couple said read register to said first column line according to second select information.

4 more elements

A serial access memory comprising:

a first memory array including a first memory cell and a pair of first bit lines, said first memory cell being selectively coupled to a corresponding bit line of said pair of first bit lines according to a voltage level of a first word line;
a second memory array including a second memory cell and a pair of second bit lines, said second memory cell being selectively coupled to a corresponding bit line of said pair of second bit lines according to a voltage level of a second word line;
a pair of column lines selectively coupled to said pair of first bit lines or said pair of second bit lines, said pairs of first and second bit lines being located between the column lines of said pair of column lines;
a coupling control circuit that provides control to selectively couple said pair of column lines to said pair of first bit lines or said pair of second bit lines according to a first select information;
a first register selectively coupled to said pair of first column lines;
and
a control circuit that provides control to selectively couple said first register to at least one column line of said pair of column lines according to a second select information.

4 more elements

Dependencies are inferred from the claim text.