Architecture, method(s) and circuitry for low power memories

A memory array comprising one or more blocks of 2 Meg SRAM cells, each block comprising:

• means for providing an address path configured to consume a maximum average operating current of approximately 2.38 mA;
• means for providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA;
• means for providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA;
• and
• means for providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA, wherein said memory array comprises at least 2 Meg of SRAM cells.

A method for providing one or more blocks of 2 Meg of SRAM cells each having a maximum average operating current of approximately 9.43 mA comprising the steps of:

• (A) providing an address path configured to consume a maximum average operating current of approximately 2.38 mA;
• (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA;
• (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA;
• and
• (D) providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA.