Adjustable current mode differential amplifier for multiple bias point sensing of MRAM having equi-potential isolation

A sensing circuit for determining the logic state of a selected memory cell in a resistive memory array, using a reference cell previously set to a known logic state, comprising:

• (a) a first bias voltage source for applying a first bias voltage to the memory cell and the reference cell;
• (b) a first sensing device for sensing a first memory cell voltage associated with the memory cell and a first reference cell voltage associated with the reference cell, both at the first bias voltage;
• (c) an equi-potential isolation circuit for applying a substantially equal voltage to both sides of each unselected memory cell;
• (d) an adjusting device for modifying the first memory cell voltage and/or first reference cell voltage so that the first reference cell voltage is approximately equal to the first memory cell voltage;
• (e) a second bias voltage source for applying a second bias voltage to the memory cell and the reference cell;
• (f) a second sensing device for sensing a second memory cell voltage associated with the memory cell and a second reference cell voltage associated with the reference cell, both at the second bias voltage;
• and
• (g) a comparing circuit for comparing the difference between the second memory cell voltage and the second reference cell voltage to determine the logic state of the memory cell.

A method of determining the logic state of a memory cell in a resistive memory array relative to a reference cell having a pre-selected logic state, comprising:

• (a) sensing a first memory cell voltage associated with the memory cell when a first bias voltage is impressed on the memory cell and sensing a second memory cell voltage associated with the memory cell when a second bias voltage is impressed on the memory cell;
• (b) sensing a first reference cell voltage associated with the reference cell when the first bias voltage is impressed on the reference cell and sensing a second reference cell voltage associated with the reference cell when the second bias voltage is impressed on the reference cell;
• (c) applying an equi-potential isolation voltage to both sides of each unselected memory cell;
• (d) modifying the first memory cell voltage and/or the first reference cell voltage to make the first memory cell voltage approximately equal to the first reference cell voltage;
• and
• (e) determining the difference between the second memory cell voltage and the second reference cell voltage in order to determine the logic state of the memory cell.

A method for determining the logic state of a selected memory cell in a resistive memory array, using a reference cell previously set to a known logic state, comprising:

• (a) applying a first bias voltage to the selected memory cell and the reference cell;
• (b) measuring a first memory cell voltage associated with the selected memory cell and a first reference cell voltage associated with the reference cell, both at the first bias voltage;
• (c) adjusting the first memory cell voltage and/or first reference cell voltage so that the first reference cell voltage is approximately equal to the first memory cell voltage;
• (d) applying a second bias voltage to the memory cell and the reference cell;
• (e) measuring a second memory cell voltage associated with the memory cell and a second reference cell voltage associated with the reference cell, both at the second bias voltage;
• (f) applying an equi-potential isolation voltage to both sides of each unselected memory cell;
• (g) comparing the difference between the second memory cell voltage and the second reference cell voltage to determine the logic state of the memory cell.