Sense amplifier control circuit of semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorDaisuke Kato
Life of this patent
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Abstract
A sense amplifier section of a semiconductor memory device includes a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array. The sense amplifier section is configured to control the transfer of data to or from the memory cell array via the bit line pairs. The sense amplifier section includes an array of layout units respectively including circuit portions of sense amplifiers, wherein the layout units are disposed in the array of layout units at intervals smaller than intervals of the bit line pairs.
Claims14
A sense amplifier section of a semiconductor memory device including a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array, the sense amplifier section being configured to control the transfer of data to or from the memory cell array via the bit line pairs, the sense amplifier section comprising:
- an array of layout units respectively including circuit portions of sense amplifiers formed in a well region, wherein none of the layout units include any contacts for biasing the well region;
- and
- a contact disposed outside of the layout units and configured to bias the well region.
A sense amplifier section of a semiconductor memory device including a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array, the sense amplifier section being configured to control the transfer of data to or from the memory cell array via the bit line pairs, the sense amplifier section comprising:
- an array of layout units directly connected to the bit line pairs and respectively including circuit portions of sense amplifiers, wherein the layout units are disposed in the array of layout units at intervals smaller than intervals of the bit line pairs.
A sense amplifier section of a semiconductor memory device including a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array, the sense amplifier section being configured to control the transfer of data to or from the memory cell array via the bit line pairs, the sense amplifier section comprising:
- an array of sense amplifiers disposed at intervals smaller than intervals of the bit line pairs;
- and
- a varying region, in which the intervals of the sense amplifiers are obtained by changing the intervals of the bit line pairs formed in a portion in contact with a boundary between the sense amplifier section and the memory cell array.
Dependencies are inferred from the claim text.