Memory device tester and method for testing reduced power states
AssigneeMicron Technology, Inc.
InventorsMatthew R. Harrington, Van C. Huynh, Adin E. Hyslop
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AssigneeMicron Technology, Inc.
InventorsMatthew R. Harrington, Van C. Huynh, Adin E. Hyslop
Estimating the term…
A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.
A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:
A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:
A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:
A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:
A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:
A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:
A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:
Dependencies are inferred from the claim text.