Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture

A method for implementing a column redundancy swapping operation for a memory array configured into a plurality of individual micro-cells, the method comprising:

• storing fuse information for each individual micro-cell, said fuse information indicative of the presence of any defective column elements therein;
• decoding a read bank address corresponding to a first micro-cell accessed for a read operation;
• decoding a write bank address corresponding to a second micro-cell accessed for a write operation, said second micro-cell capable of being accessed simultaneously with said first micro-cell;
• comparing said decoded read bank address to specific fuse information corresponding to said first micro-cell;
• and
• comparing said decoded write bank address to specific fuse information corresponding to said second micro-cell;
• wherein, if there is at least one defective column element contained within said first micro-cell, then generating an internal column address corresponding to said at least one defective column element in said first micro-cell;
• and
• if there is at least one defective column element contained within said second micro-cell, then generating an internal column address corresponding to said at least one defective column element in said second micro-cell.