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US 6,674,675 B2Granted
Semiconductor device with flexible redundancy system
AssigneeKabushiki Kaisha Toshiba
InventorSatoru Takase
Life of this patent
Estimating the term…
Abstract
A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.
Claims25
A semiconductor device comprising:
- a first memory block having memory cells;
- a second memory block having memory cells, the second memory block configured to be in an active state at a time when the first memory block is in an active state;
- a plurality of first redundancy units for replacement of first defective memory cells in the first memory block;
- a plurality of second redundancy units for replacement of second defective memory cells in the second memory block;
- and
- a plurality of storage elements configured to store defective addresses assigned to defective memory cells, and also store mapping information for designating any redundancy units of the first redundancy units and the second redundancy units.
3 more elements
A semiconductor device comprising:
- a plurality of memory blocks, each memory block being activated independently at a time when another memory block is in an active state;
- a plurality of redundancy units for replacement of defective memory cells in the plurality of memory blocks;
- and
- a plurality of storage elements configured to store defective addresses assigned to defective memory cells, and also store mapping information;
- wherein the storage elements replace defective memory cells of any of the plurality of memory blocks with the redundancy units in accordance with the mapping information.
2 more elements
A semiconductor device comprising:
- a plurality of memory blocks, each memory block being activated independently at a time when another memory block is in an active state;
- a plurality of redundancy units for replacement of defective memory cells in the plurality of memory blocks;
- and
- a plurality of storage elements configured to store defective addresses assigned to defective memory cells, and also store mapping information for designating the redundancy units included in any of the plurality of memory blocks.
1 more element
A semiconductor device comprising:
- a plurality of memory blocks, each memory block being activated independently at a time when another memory block is in an active state;
- a plurality of redundancy units for replacement of defective memory cells in the plurality of memory blocks;
- and
- a plurality of storage elements configured to store defective addresses assigned to defective memory cells, and also store mapping information for designating the redundancy units included in any of the plurality of memory blocks,
- wherein one of the redundancy units replaces defective cells of any one of the plurality of memory blocks.
2 more elements
A semiconductor device comprising:
- a plurality of memory blocks each having memory cells;
- a plurality of redundancy units for replacement of defective memory cells in the plurality of memory blocks;
- and
- a plurality of storage elements configured to store defective addresses assigned to defective memory cells included in the memory blocks, mapping information for designating the redundancy units, and address information to select the memory block.
1 more element
A semiconductor device comprising:
- a plurality of memory blocks each having memory cells;
- a number N of redundancy units for replacement of defective memory cells in the plurality of memory blocks;
- and
- a plurality of storage elements configured to store defective addresses assigned to the defective memory cells;
- wherein each of the defective addresses consists of M bits, and the number of the plurality of storage elements is less than M×N.
2 more elements
A semiconductor device comprising:
- a plurality of memory blocks each having memory cells;
- a number N of redundancy units for replacement of defective memory cells in the plurality of memory blocks;
- and
- a plurality of storage elements configured to store defective addresses assigned to the defective memory cells, the plurality of storage elements being for the replacement of defective memory cells in any of the plurality of memory blocks.
1 more element
A semiconductor device comprising:
- a plurality of memory blocks each having memory cells;
- a number N of redundancy units for replacement of defective memory cells in the plurality of memory blocks;
- and
- a plurality of storage elements configured to hold L bits and store defective addresses assigned to the defective memory cells;
- wherein each of the defective addresses consists of M bits, and L is less than MxN.
2 more elements
Dependencies are inferred from the claim text.