Circuit for lines with multiple drivers

An apparatus comprising:

• a first plurality of transistors, each of the first plurality of transistors having a control terminal coupled to receive a respective one of a first plurality of dynamic data signals, wherein each of the first plurality of transistors is coupled to a first node and is configured to drive a first state on the first node responsive to an assertion of the respective one of the first plurality of dynamic data signals;
• a second transistor coupled to the first node and having a second control terminal, the second transistor configured to drive a second state on the first node responsive to a signal on the second control terminal;
• and
• a circuit coupled to generate the signal on the second control terminal and coupled to receive, a second plurality of dynamic data signals, wherein each of the second plurality of dynamic data signals is a complement of a respective one of the first plurality of dynamic data signals, and wherein the circuit is configured to activate the second transistor responsive to an assertion of one of the second plurality of dynamic data signals.

An apparatus comprising:

• a first transistor having a first control terminal coupled to receive a first dynamic data signal, wherein the first transistor is coupled to a first node and is configured to drive a first state on the first node responsive to an assertion of the first dynamic data signal;
• a second transistor coupled to the first node and having a second control terminal, the second transistor configured to drive a second state on the first node responsive to a signal on the second control terminal;
• a circuit coupled to generate the signal on the second control terminal and coupled to receive a second dynamic data signal, the second dynamic data signal being a complement of the first dynamic data signal, wherein the circuit is configured to activate the second transistor responsive to an assertion of the second dynamic data signal;
• and
• a keeper coupled to the first node and configured to retain a previous state of the first node responsive to a deassertion of each of the first dynamic data signal and the second dynamic data signal.

A memory array comprising:

• a plurality of banks of memory, each bank configured to output a first dynamic data signal indicative of a bit stored in the bank and a second dynamic data signal indicative of the complement of the bit;
• and
• a bank select circuit coupled to receive the first dynamic data signal and the second dynamic data signal from each of the plurality of banks and configured to output a selected bit responsive to the first dynamic data signal and the second dynamic data signal from each of the plurality of banks, the bank select circuit comprising:
• a first plurality of transistors, each having a control terminal coupled to receive the first dynamic data signal from a respective one of the plurality of banks, wherein each of the first plurality of transistors is coupled to a first node and is configured to drive a first state on the first node responsive to an assertion of the first dynamic data signal;
• a second transistor coupled to the first node and having a second control terminal, the second transistor configured to drive a second state on the first node responsive to a signal on the second control terminal;
• and
• a circuit coupled to generate the signal on the second terminal and coupled to receive the second dynamic data signal from each of the plurality of banks, wherein the circuit is configured to activate the second transistor responsive to an assertion of the second dynamic data signal from one of the plurality of banks.

A computer accessible medium comprising one or more data structures representing:

• a first plurality of transistors, each having a control terminal coupled to receive a respective one of a first plurality of dynamic data signals, wherein each of the first plurality of transistors is coupled to a first node and is configured to drive a first state on the first node responsive to an assertion of the respective one of the first plurality of dynamic data signals;
• a second transistor coupled to the first node and having a second control terminal, the second transistor configured to drive a second state on the first node responsive to a signal on the second control terminal;
• and
• a circuit coupled to generate the signal on the second terminal and coupled to receive a second plurality of dynamic data signals, each of the second plurality of dynamic data signals being a complement of a respective one of the first plurality of dynamic data signals, wherein the circuit is configured to activate the second transistor responsive to an assertion of one of the second plurality of dynamic data signals.

A computer accessible medium comprising one or more data structures representing:

• a source circuit configured to generate a first dynamic data signal and a second dynamic data signal that is a complement of the first dynamic data signal;
• a first transistor having a first control terminal coupled to receive the first dynamic data signal, wherein the first transistor is coupled to a first node and is configured to drive a first state on the first node responsive to an assertion of the first dynamic data signal;
• a second transistor coupled to the first node and having a second control terminal, the second transistor configured to drive a second state on the first node responsive to a signal on the second control terminal;
• and
• a circuit coupled to receive the second dynamic data signal, and configured to generate the signal on the second control terminal responsive to the second dynamic data signal, wherein the circuit is configured to activate the second transistor responsive to an assertion of the second dynamic data signal.