Nonvolatile memory structures and access methods
AssigneeMosel Vitelic, Inc.
InventorsHsing T. Tuan, Li-Chun Li, Vei-Han Chan
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Abstract
In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.
Claims15
A circuit comprising:
- a plurality of rows of nonvolatile memory cells, each memory cell having a first semiconductor region, a first gate for controlling a conductivity of the first semiconductor region, a second gate insulated from the first gate, and a first node through which a current flows to or from the first semiconductor region;
- circuitry for driving the first and second gates and the first nodes into respective states to perform a first memory access operation to access one or more memory cells, wherein during the first access operation:
- (a) the first gates within each row are in the same state, the second gates within each row are in the same state, and the first nodes within each row are in the same state;
- (b) the first gates within each row being accessed are in a different state than the first gates of each row not being accessed;
- (c) for some row RI being accessed and some rows R2, R3 which are not being accessed, the second gates of the rows R1, R2 are in the same state, the first nodes of the rows R1, R3 are in the same state, but the second gates of the rows R1, R3 are not in the same state.
A semiconductor integrated circuit comprising a plurality of rows of nonvolatile memory cells, each memory cell having a first source/drain region, a second source/drain region, a semiconductor region between the first and second source/drain regions, a select gate, a control gate, and a floating gate;
- wherein within each row of the memory cells (a) all of the first source/drain regions are connected together, (b) all of the select gates are connected together, and (c) all of the control gates are connected together;
- wherein the first source/drain regions of each row are connected to the first source/drain regions of at least one other row, and the control gates of each row are connected to the control gates of at least one other row, but any two rows that have their control gates connected together do not have their first source/drain regions connected together.
Dependencies are inferred from the claim text.