Read circuit on nonvolatile semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorsTamio Ikehashi, Kenichi Imamiya, Junichiro Noda
Life of this patent
Estimating the term…
Abstract
An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.
Claims15
A read circuit of a nonvolatile semiconductor memory comprising:
- at least one sense amplifier;
- and
- a read control signal generating circuit for supplying a first signal to said at least one sense amplifier,
- wherein said at least one sense amplifier has a first current path comprised of a first P-channel MOS transistor having a source electrically connected to a first power supply node and a gate applied with said first signal, and a first N-channel MOS transistor connected between a drain of said first P-channel MOS transistor and a memory cell and having a gate applied with a second signal, and
- said read control signal generating circuit has a second current path comprised of a second P-channel MOS transistor having a gate and a drain connected to the gate of said first P-channel MOS transistor and a source electrically connected to said first power supply node, and a second N-channel MOS transistor connected between the drain of said second P-channel MOS transistor and a reference cell and having a gate applied with a third signal.
Dependencies are inferred from the claim text.