Device and method for timing the reading of a nonvolatile memory with reduced switching noise

A nonvolatile memory device, comprising:

• a memory array having an output;
• a data-sensing stage having a data input connected to said memory array, a sensing-enabling input, and an output;
• an output stage having an input connected to said output of said data-sensing stage and an enabling input receiving a sync signal, said output stage being enabled at a first switching edge of said sync signal;
• and
• a read-timing stage having an output connected to said sensing-enabling input of said data-sensing stage;
• wherein said read-timing stage has a sync input receiving said sync signal and generates said sensing-latch signal not before a preset time interval from said first switching edge of said sync signal.

A method for reading a nonvolatile memory comprising a data-sensing stage and an output stage, the method comprising the steps of:

• supplying a sensing-latch signal to said data-sensing stage;
• supplying a sync signal to said output stage;
• and
• enabling said output stage at a first switching edge of said sync signal,
• generating said sensing-latch signal not before a preset time interval from said first switching edge of said sync signal.

An output timing device comprising:

• a reset generator having an output at which a reset signal is produced;
• a sensing latch request circuit having an input receiving an activation signal, and an output producing a latch request signal in response to the activation signal;
• a data-hold circuit having an input coupled to the output of the sensing latch request circuit, and output transmitting a sensing request signal for controlled activation of a sensing stage, and a reset input coupled to the output of the reset generator;
• and
• an extension circuit having an input receiving the activation signal, an output transmitting a delayed signal for controlling activation of an output stage coupled to the sensing stage, and a reset input receiving the output of the reset generator, the delayed signal being a delayed version of the activation signal for controlling activation of the output stage.