Methods for saving power and area for content addressable memory devices
AssigneeUniram Technology Inc.
InventorJeng-Jye Shau
Life of this patent
Estimating the term…
Abstract
Using 6 transistor memory cell to replace prior art 10 transistor binary content addressable memory (CAM) cells, and using 10 transistor ternary CAM (TCAM) cell to replace prior art 16 transistor TCAM cells, the present invention provided significant cost saving for high density CAM products. The power consumption problems of prior art high density CAM devices are solved by novel zoned lookup mechanism. For a high density CAM storing sorted data, lookup mechanisms of the present invention can reduce power consumption by two orders of magnitudes.
Claims24
A content addressable memory (CAM) cell comprising:
- four transistors configured as a back-to-back inverter for forming a bi-stable memory having a first and a second memory nodes for storing a pair of stored complimentary binary bits;
- and
- a fifth and a sixth transistors connected to said first and said second memory nodes respectively for receiving a pair of input complimentary binary bits therefrom for providing a control of inverting said pair of store complimentary binary bit stored in said first and second memory nodes to generate a match-mismatch signal between said pair of input complimentary binary bits and said pair of stored complimentary binary bits.
A content addressable memory (CAM) cell comprising:
- a first set of four transistors configured as a back-to-back inverter for forming a bi-stable memory having a first and a second memory nodes for storing a first pair of stored complimentary binary bits;
- a second set of four transistors configured as a back-to-back inverter for forming a bi-stable memory having a third and a fourth memory nodes for storing a second pair of stored complimentary binary bits;
- a single-bit-line-write (SBLW) voltage means connected to said first and second sets of four transistors for providing a SBLW voltage cvdd;
- and
- a ninth and a tenth transistors connected to said first and said fourth memory nodes respectively for receiving a pair of input complimentary binary bits therefrom for providing a control of applying a SBLW operation for inverting said pair of store complimentary binary bit stored in said first and fourth memory nodes to generate a match-mismatch-don't-care ternary signal between said pair of input complimentary binary bits and said first and second pairs of stored complimentary binary bits.
A content addressable memory (CAM) cell comprising:
- a memory circuit having a memory node for storing a first digital data;
- and
- a data controlled pass-gate means connected to said memory node for receiving and writing a second digital data to said memory node and for comparing said second digital data with said first digital data.
A content addressable memory (CAM) device comprising:
- a plurality of CAM entry each comprising a plurality of CAM cells for storing a set of stored data for comparison with a set of input data;
- each of said CAM entries is divided into a plurality of CAM sections each storing a subset of said stored data;
- a circuit for each of said CAM sections for sensing a match-mismatch between said subset of said stored data and a corresponding subset of said input data.
A content addressable memory (CAM) device comprising:
- a plurality of CAM entry each comprising a plurality of CAM cells for storing a set of stored data for comparison with a set of input data;
- each of said CAM entries is divided into a plurality of CAM sections each storing a subset of said stored data and nearby CAM sections are grouped into CAM zones;
- a circuit for each of said CAM sections for sensing a match-mismatch between said subset of said stored data in said section and a corresponding subset of said input data;
- and
- a logic circuit connected to said circuit for each of said CAM sections for sensing an all-missed condition in each of said zones and for stopping a lookup operation when an all-missed condition is sensed.
A content addressable memory (CAM) device comprising:
- a plurality of CAM entries each comprising a plurality of CAM cells for storing a set of stored data for comparison with a set of input data;
- a partial lookup means for carrying out a partial lookup by comparing a subset of said input data with a corresponding subset of stored data.
Dependencies are inferred from the claim text.