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US 6,674,647 B2Granted
Low or no-force bump flattening structure and method
AssigneeInternational Business Machines Corporation
InventorsMark V. Pierson, Ajit K. Trivedi
Life of this patent
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Abstract
Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.
Claims5
An electronic package, comprising:
- a first substrate;
- a plurality of pads formed on the first substrate, each pad having a raised flat surface;
- a plurality of first solders each formed on the raised surface of a corresponding one of the plurality of pads and having a top concave surface and a bottom flat surface covering the raised flat surface of the corresponding pad;
- a second substrate facing the first substrate;
- and
- a plurality of a second solders formed on the second substrate corresponding to the plurality of first solders, each second solder having a convex top surface matching the concave surface of the corresponding first solder,
- wherein the plurality of first solders are softer than the plurality of second solders to allow each of the plurality of first solders to match with the convex top surface of each of the corresponding plurality of second solders such that a personalized fit is provided between each of the plurality of first and second solders.
4 more elements
Dependencies are inferred from the claim text.