Memory system for accelerating graphics operations within an electronic device
AssigneeSTMicroelectronics S.r.l.
InventorsBhaskar Chowdhuri, Kanwal Preet Singh Banga, Frank Palazzolo, Jr., Ugo Zampieri
Life of this patent
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Abstract
The present invention relates to a system and method for accelerating graphics. The system includes a memory device for accelerating graphics operations within an electronic device. A memory controller is used for controlling pixel data transmitted to and from the memory device. A cache memory is electrically coupled to the memory and is dynamically configurable to a selected usable size to exchange an amount of pixel data having the selected usable size with the memory controller. The memory device may be an SDRAM. The cache memory may also comprise a plurality of usable memory areas or tiles.
Claims29
A system including a memory device for accelerating line drawing graphics operations within an electronic device, the system comprising:
- a memory controller for controlling pixel data transmitted to and from the memory device;
- and
- a cache memory electrically coupled to the memory controller, the cache memory being dynamically, two-dimensionally configurable to a selected usable size to exchange an amount of data associated with line drawing having the selected usable size with the memory controller, said memory controller operable to change the usable size of the cache memory during graphics operations in response to receiving independent parameters received by the cache memory defining a height and width to form a tile of the selected usable size.
A method for accelerating line drawing graphics operations within an electronic device, the method comprising the steps of:
- configuring a two-dimensional cache memory to a first selected size usable for graphics operations;
- receiving independent parameters defining a height and width;
- changing the first selected size of the two-dimensional cache memory to a second selected size during a graphics operation based on the independent parameters to form a tile of the second selected size;
- and
- exchanging an amount of data associated with line drawing having the second selected size with a memory device.
A method for accelerating line drawing graphics operations within an electronic device, said method comprising the steps of:
- receiving a request for accessing data relating to a pixel of a line;
- determining a two-dimensional pseudo tile in which the pixel of the line is located;
- selectively retrieving data associated with the line from a memory device corresponding to the pseudo tile;
- based on the data associated with the line, generating independent parameters defining a height and a width for changing a tile configuration within a cache memory;
- storing the data associated with the line from the pseudo tile in the changed tile configuration within the cache memory;
- and
- providing the requested pixel data from the cache memory in response to the request.
A system for accelerating line drawing graphics operations within an electronic device, the system comprising:
- a cache memory arranged in a tile configuration, said cache memory capable of having data stored in said cache memory being selectively altered, the tile configuration of the cache memory being based on at least two independent parameters being received;
- a memory arranged in a scan line configuration electrically coupled to the cache memory;
- and
- means for enabling the cache memory to alter at least one datum of the data associated with a line graphic stored in the cache memory during a line drawing graphics operation.
Dependencies are inferred from the claim text.