Method and apparatus for improving performance of an accelerated graphics port (AGP) device

Abstract

A method and apparatus for improving performance of an AGP device is provided. In one embodiment of the invention, a second-level cache is provided for a TLB, and part of the data or part of the address that is not otherwise used for determining a TLB entry is divided by a prime number to determine which TLB entry to allocate. One embodiment of the invention provides the ability to load multiple cache lines during a single memory access without incurring additional transfer, storage, or management complexities. The full number of bits of each memory access may be used to load cache lines. One embodiment of the invention loads multiple cache lines for translations of consecutive ranges of addresses. Since the translations included in the multiple cache lines cover consecutive ranges of addresses, the relationship between the multiple cache lines loaded for a single memory access is understood, and additional complexity for cache management is avoided. Loading of multiple cache lines for translations of consecutive ranges of addresses also improves performance by increasing the number of translations available in the TLB. Moreover, locality of reference tends to make translations for consecutive ranges of addresses more likely to be relevant than translations for distant ranges of addresses.

Dependencies are inferred from the claim text.