Pulse width modulation analog to digital conversion

An analog-to-digital converter comprising:

• a) a pulse width modulator, the pulse width modulator receiving an analog signal and outputting a pulse-width-modulated signal having a duty cycle responsive to the analog signal, wherein the pulse width modulator includes a comparator having an input and an output and includes an operational amplifier having a first input, a second input, and an output, wherein the operational amplifier output is coupled to the comparator input and wherein the comparator output is fed back to the operational amplifier first input, and wherein the comparator output is fed back to the operational amplifier input through a first inverter;
• and
• b) a duty cycle mechanism, the duty cycle mechanism receiving the pulse-width-modulated signal and determining a digital value proportional to the analog signal from the duty cycle of the pulse-width-modulated signal.

An analog-to-digital converter comprising:

• a) a pulse width modulator, the pulse width modulator receiving an analog signal and outputting a pulse-width-modulated signal having a duty cycle responsive to the analog signal, wherein the pulse width modulator includes a comparator having an input and an output and includes an operational amplifier having a first input, a second input, and an output, wherein the operational amplifier output is coupled to the comparator input and wherein the comparator output is fed back to the operational amplifier first input, and wherein the comparator output is further fed back to the comparator input with a feedback path, and further comprising a first resistor coupled between the op-amp output and the comparator input, and further comprising a second resistor in the feedback path coupled between the comparator output and the comparator input, and wherein the first and second resistors are selected to provide hysteresis in the comparator output;
• and
• b) a duty cycle mechanism, the duty cycle mechanism receiving the pulse-width-modulated signal and determining a digital value proportional to the analog signal from the duty cycle of the pulse-width-modulated signal.

An analog-to-digital converter comprising:

• a) a pulse width modulator, the pulse width modulator receiving an analog signal and outputting a pulse-width-modulated signal having a duty cycle responsive to the analog signal;
• and
• b) a duty cycle mechanism, the duty cycle mechanism receiving the pulse-width-modulated signal and determining a digital value proportional to the analog signal from the duty cycle of the pulse-width-modulated signal, wherein the duty cycle mechanism includes an active counter to count enabled portions of the pulse-width modulated signal.

An analog-to-digital converter comprising:

• a) a pulse width modulator, the pulse width modulator receiving an analog signal and outputting a pulse-width-modulated signal having a duty cycle responsive to the analog signal;
• and
• b) a duty cycle mechanism, the duty cycle mechanism receiving the pulse-width-modulated signal and determining a digital value proportional to the analog signal from the duty cycle of the pulse-width-modulated signal, wherein the duty cycle mechanism is implemented in an FPGA.