US 6,674,331 B2 · Method and apparatus for simplified tuning of a two-point modulated PLL

Abstract

A method and apparatus are disclosed for tuning a voltage controlled oscillator (VCO) having two point modulation used in a phase lock loop modulation system. A loop correction voltage applied to a first modulation input of the VCO when a first modulation signal, e.g., +1, is applied to a second modulation input of the VCO is compared to a loop correction voltage applied to the first modulation input when a second modulation signal, e.g., −1, is applied to the second modulation input of the VCO. The comparison produces a correction signal used to adjust the signal level of at least one of the signals, e.g., the second modulation input signal, applied to the two modulation inputs of the VCO.

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Drawings

Claims39

Dependent claims

A modulation system comprising:

a phase lock loop comprising a voltage controlled oscillator which is responsive to two signals which affect an output from said voltage controlled oscillator;
one signal comprising a loop correction signal and the other signal comprising a gain corrected modulation input signal;
and
a modulation gain correction circuit comprising a comparator for comparing first and second filtered signals developed by the phase lock loop in response to respective first and second modulation inputs and developing a gain correction signal from the comparison, said gain correction signal being used to scale an applied input modulation signal to produce the gain corrected modulation input signal.

1 more element

A modulation system comprising:

a phase lock loop comprising:
a phase detector having first and second input, said first input for receiving a reference signal;
a loop filter coupled to an output of the phase detector;
a voltage controlled oscillator coupled to receive a loop correction output signal of said loop filter and a scaled input modulation signal, said voltage controlled oscillator providing a modulated output signal;
a frequency divider for dividing the output of said voltage controlled oscillator and providing a frequency divided output to said second input of said phase detector;
a scaling circuit for scaling an applied input modulation signal in accordance with a gain correction signal to provide said scaled input modulation signal;
and
a gain correction circuit, said gain correction circuit produces said gain correction signal based on a comparison of a loop correction output signal produced when said voltage controlled oscillator receives an unscaled first level modulation signal with a loop correction output signal produced when said voltage controlled oscillator receives an unscaled second level modulation signal.

5 more elements

Dependencies are inferred from the claim text.

Description5,080 words

Summary939 words

#The present invention relates to a method and apparatus for tuning a voltage controlled oscillator (VCO) within a two-point modulated phase lock loop (PLL) system.

#Phase lock loop (PLL) modulated transmission systems are known in which a carrier frequency, set by a VCO as the center frequency of the loop, can be modulated by applying a signal to a single point in the loop.

#Single point modulation circuits modulate the VCO by connecting the modulating signal to one side of the loop filter or the other. With the pre-loop filter connection circuit, the modulating signal is low-pass filtered by the loop as it is modulated onto the carrier. Thus components of the modulating signal that are higher than the loop bandwidth will be suppressed. Unless there is no significant energy in the modulating signal above the loop bandwidth, the signal will suffer some loss (distortion) during the modulation.

Brief description of the drawings9 figures

#FIG. 1 is a block diagram of an exemplary PLL modulation system which may employ the invention;

#FIG. 2 is a block diagram of a gain correction circuit which may be used with the FIG. 1 circuit;

#FIG. 3 is a process sequence for balancing the Vkvco and Vkmod signal gains using the FIG. 1 and FIG. 2 circuits;

Detailed description3,982 words

#Referring to the drawings, FIG. 1 illustrates a PLL system for use in binary frequency shift keying (BFSK) scheme modulating a carrier signal to produce a modulated output signal Fout. The carrier center frequency is set by the VCO and frequency modulation of this carrier occurs in response to a signal applied to a modulation input terminal 15. The PLL includes a phase detector 25, loop filter 27, a VCO 31 for receiving the loop correction modulating signal Vkvco 29 and a gain corrected modulation signal input Vkmod 33 and providing the output signal Fout, and a frequency divider 21 for dividing by the Fout signal by a scalable factor N which is then applied to phase detector 25 which also receives a reference signal 23. A scaling circuit 37 is provided which receives a gain correction input signal 35 which is used to scale the gain of the modulation signal 15 input into the scaling circuit 37 thereby producing a gain corrected modulation input signal Vkmod 33 for input to the VCO 31.

#A carrier channel input 13 is provided which is used to program divider 21 to divide the Fout signal by an appropriate factor N for a given channel carrier frequency to produce a loop frequency which is input to phase detector 25 for comparison with reference frequency signal 23. The carrier channel input 13 is provided by a control circuit 18. The carrier channel input 13 is a number of a digital value which is used to determine the base carrier frequency in the Fout signal. For example, if the center frequency of Fout is to be 100 Mhz and the reference signal 23 is 10 Mhz, then the carrier channel input value would be the digital value corresponding to 11. The carrier channel input is also adjusted by the value of the applied modulation input 15 with an adder 17. Alternatively the modulation input to the adder 17 can also be accomplished using a scaler which serves as a frequency deviation input for +1 and −1 deviation which would scale a +1 to a number representing a desired positive deviation in frequency and −1 to a number representing a desired negative deviation in frequency.

#A fractionalization circuit 19 produces an average value of the carrier channel input as adjusted by the modulation input 15. The N in the frequency divider 21 is obtained from the fractionalization circuit 19 output to create the desired average loop frequency value that is input into the phase detector 25. Note that in this example, N does not equal carrier+modulation. Channel selection circuitry can incorporate a circuit which derives a sequence of divisor factors such that the average of said sequence of divisor factors is equal to the sum of the received signals.

Facts

Application

09/986,669Filed 9 Nov 2001

Published

US 2003/0090328 A115 May 2003

Granted

6 Jan 2004

Term ended

26 Nov 2021

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 17 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification5 codes

H03C 3/0958
Using a phase locked loop: applying frequency modulation by varying the characteristics of the voltage controlled oscillator
H03C 3/0925
With frequency divider or counter in the loop: applying frequency modulation at the divider in the feedback loop
H03C 3/0933
With frequency divider or counter in the loop: using fractional frequency division in the feedback loop of the phase locked loop
H03C 3/0941
Using a phase locked loop: applying frequency modulation at more than one point in the loop

Timeline

9 Nov 2001Application filedUS 09/986,669
9 Nov 2001Assigned to Agere Systems Inc.assignment of assignor's interest
15 May 2003PublishedUS 2003/0090328 A1
6 Jan 2004GrantedUS 6,674,331 B2
8 May 2014Assigned to Deutsche Bank AG New York Branch, AS Collateral Agentpatent security agreement
3 Apr 2015Assigned to Avago Technologies General IP (Singapore) Pte. Ltd.assignment of assignor's interest
2 Feb 2016Assigned to Lsi Corporation, Agere Systems LLCtermination and release of security interest in patent rights (releases rf 032856-0031)
11 Feb 2016Assigned to Bank of America, N.A., AS Collateral Agentpatent security agreement
3 Feb 2017Assigned to Avago Technologies General IP (Singapore) Pte. Ltd.termination and release of security interest in patents
4 Oct 2018Assigned to Avago Technologies International Sales Pte. Limitedmerger
5 Nov 2018Assigned to Avago Technologies International Sales Pte. Limitedcorrective assignment to correct the effective date of merger previously recorded on reel 047195 frame 0026. assignor(s) hereby confirms the merger.
26 Nov 2021Term endedEstimated, includes 17 days of adjustment

Method and apparatus for simplified tuning of a two-point modulated PLL

Life of this patent

Method and apparatus for simplified tuning of a two-point modulated PLL

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims39

Description5,080 words

Drawings

Classification5 codes

Life of this patent

Description5,080 words