Recording clock generation circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsTakahiro Bokui, Takahiro Ochi, Yoshinori Miyada, Yutaka Murata
Life of this patent
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Abstract
A recording clock generation circuit includes a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal; a first filter for smoothing an output from the first phase comparator; a VCO circuit for oscillating in accordance with the output smoothed by the first filter; a frequency divider for dividing a frequency of an output from the VCO circuit; a phase adjusting circuit for adjusting a phase of an output from the frequency divider; and a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.
Claims2
A recording clock generation circuit, comprising:
- a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal;
- a first filter for smoothing an output from the first phase comparator:
- a VCO circuit for oscillating in accordance with the output smoothed by the first filter;
- a frequency divider for dividing a frequency of an output from the VCO circuit;
- a phase adjusting circuit for adjusting a phase of an output from the frequency divider and providing the PLL internal signal based thereon;
- and
- a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.
Dependencies are inferred from the claim text.