US 6,674,319 B1Granted

Power down mode signaled by differential transmitter's high-Z state detected by receiver sensing same voltage on differential lines

AssigneePericom Semiconductor Corp.

InventorHide Hattori

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Abstract

A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines. A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an equal-voltage detector that generates a power-down signal when the differential lines are at equal voltages for a period of time. The period of time can be greater than the cross-over time during normal switching to prevent false power-downs during normal switching. Standard differential drivers can signal power-down using the high-impedance state, which is detected by equal voltages on the differential lines. A sensitive dual-differential amplifier and a simpler detector are disclosed.

Claims7

Dependent claims

A power-down circuit comprising:

a differential pair of lines that are connected together by a shunt resistor that equalizes a first voltage on a first differential line with a second voltage on a second differential line when a differential transmitter is powered down in a high-impedance state;
a first n-channel sensing transistor having a gate driven by the first differential line, a drain coupled to a power supply, and a source coupled to a first source node;
a second p-channel sensing transistor having a gate driven by the second differential line, a drain coupled to a sense node, and a source coupled to the first source node;
a second n-channel sensing transistor having a gate driven by the second differential line, a drain coupled to the power supply, and a source coupled to a second source node;
a first p-channel sensing transistor having a gate driven by the first differential line, a drain coupled to the sense node, and a source coupled to the second source node;
an output n-channel transistor, having a gate connected to the sense node, and a drain connected to an output representing a power-down signal;
a pull-up connected between the output and the power supply for driving the output high when the output transistor is not conducting current;
a pull-down connected between the sense node and a ground for driving the sense node low when the first and second p-channel transistors and the first and second n-channel transistors are turned-off when the first and second differential lines have voltages within a transistor threshold of each other.

5 more elements

A sensitive power-down circuit comprising:

a differential pair of lines that are connected together by a shunt resistor that equalizes a first voltage on a first differential line with a second voltage on a second differential line when a differential transmitter is powered down in a high-impedance state;
a first current source for generating a first reference current;
a first differential sense transistor having a gate receiving the first differential line, a source coupled to the first current source, and a drain coupled to a first mirror node;
a first combined sense transistor having a gate receiving the first differential line, a source coupled to the first current source, and a drain coupled to a first amplifier node;
a second combined sense transistor having a gate receiving the second differential line, a source coupled to the first current source, and a drain coupled to the first amplifier node;
a first mirror transistor having a gate and a drain coupled to the first mirror node, and a source coupled to a ground;
a second mirror transistor having a gate coupled to the first mirror node, a drain coupled to the first amplifier node, and a source coupled to the ground;
a second current source for generating a second reference current;
a second differential sense transistor having a gate receiving the second differential line, a source coupled to the second current source, and a drain coupled to a second mirror node;
a third combined sense transistor having a gate receiving the first differential line, a source coupled to the second current source, and a drain coupled to a second amplifier node;
a fourth combined sense transistor having a gate receiving the second differential line, a source coupled to the second current source, and a drain coupled to the second amplifier node;
a third mirror transistor having a gate and a drain coupled to the second mirror node, and a source coupled to the ground;
a fourth mirror transistor having a gate coupled to the second mirror node, a drain coupled to the second amplifier node, and a source coupled to the ground;
a first output transistor having a gate receiving the first amplifier node, a drain coupled to a combining node, and a source coupled to the ground;
a second output transistor having a gate receiving the second amplifier node, a drain coupled to the combining node, and a source coupled to the ground;
a pull-up device coupled between a power supply and the combining node, to pull up the combining node when the first and second output transistors are off,
wherein the combining node is pulled high by the pull-up device when the first and second differential line are at a same voltage between the power supply and the ground, the same voltage occurring when the differential transmitter is powered down in a high-impedance state.

14 more elements

Dependencies are inferred from the claim text.