US 6,674,314 B2 · Interpolating circuit, DLL circuit and semiconductor integrated circuit

Abstract

Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply. On the basis of control signals that decide the interior division ratio, the bias control unit performs control in such a manner that current-path switches are turned on and off so that first and second current values, which are the totals of current values, will flow into the first and second constant-current sources, respectively.

Claims22

Dependent claims

An interpolating circuit, receiving first and second signals, for generating an output signal having a phase corresponding to a value obtained by dividing a phase difference between the first and second signals in accordance with a preset interior division ratio, said interpolating circuit comprising a waveform synthesis unit and a bias control unit;

said waveform synthesis unit including:
a first switch element inserted between a node connected to an output terminal from which the output signal is delivered, and a first power supply;
means for placing said first switch element in an ON state when the first and second signals are both a first logic value;
a first series circuit composed by serial connection of a first current source and a second switch element placed in the ON state when the first signal is a second logic value;
and
a second series circuit composed by serial connection of a second current source and a third switch element placed in the ON state when the second signal is the second logic value;
said first series circuit and said second series circuit being connected in parallel with each other between the node connected to the output terminal and a second power supply;
said bias control unit setting current values flowing through the first and second current sources of said waveform synthesis unit respectively to values conforming to the interior division ratio.

5 more elements

An interpolating circuit, receiving first and second signals, for generating an output signal having a phase corresponding to a value obtained by dividing a phase difference between the first and second signals in accordance with a interior division ratio set by an entered control signal, said interpolating circuit comprising a waveform synthesis unit and a bias control unit;

said waveform synthesis unit including:
a first switch element inserted between a node connected to an output terminal from which the output signal is delivered, and a first power supply;
means for placing said first switch element in an ON state when the first and second signals are both a first logic value;
a first series circuit composed by serial connection of a first current source and a second switch element placed in the ON state when the first signal is a second logic value;
and
a second series circuit composed by serial connection of a second current source and a third switch element placed in the ON state when the second signal is the second logic value;
said first series circuit and said second series circuit being connected in parallel with each other between the node connected to the output terminal and a second power supply;
said bias control unit including:
means for generating first and second currents, a current-value ratio of which conform to the interior division ratio, based upon the control signal;
and
means for performing control in such a manner that currents conforming to the current values of the first and second currents flow through the first and second current sources, respectively, of said waveform synchronizer.

8 more elements

An interpolating circuit, receiving first and second signals, for generating an output signal having a phase corresponding to a value obtained by dividing a phase difference between the first and second signals in accordance with a interior division ratio set by an entered control signal, said interpolating circuit comprising a waveform synthesis unit and a bias control unit;

said waveform synthesis unit including:
a first switch element inserted into a charging path of a node connected to an output terminal from which the output signal is delivered;
means for charging the node connected to the output terminal, by turning on said first switch element when the first and second signals are both a first logic value;
and
first and second discharge paths provided to correspond to the first and second signals, respectively, and connected to the node connected to the output terminal;
a first current source and a second switch element that is turned on and off based upon the first signal, being serially inserted into said first discharge path;
a second current source and a third switch element that is turned on and off based upon the second signal, being serially inserted into said second discharge path;
and
at least one of the second switch element and third switch element being turned on to discharge said node connected to the output terminal, when at least one of the first signal and second signal is a second logic value;
said bias control unit controlling the bias of the first constant-current source and second constant-current source of said waveform synthesis unit and including:
means for generating a first current and a second current, which exhibit a current-value ratio that conforms to the interior division ratio, in response to two sets of current-path switches being turned on and off based upon the control signal;
and
means for performing control in such a manner that currents corresponding to current values of respective ones of the first current and second current flow into respective ones of the first current source and second current source of said waveform synthesis unit.

10 more elements

An interpolating circuit, receiving first and second signals, for generating an output signal having a phase corresponding to a value obtained by dividing a phase difference between the first and second signals in accordance with a division ratio set by an entered control signal, said interpolating circuit comprising a waveform synthesis unit and a bias control unit;

said waveform synthesis unit including:
a logic circuit, receiving the first and second signals, for outputting the result of a predetermined logic operation applied to the first and second signals;
a first switch element, being inserted between a node connected to an output terminal from which the output signal is delivered and a first power supply, having a control terminal for receiving an output signal from said logic circuit to turn said first switch element on and off;
a first series circuit composed by serial connection of a first current source and a second switch element having a control terminal for receiving the first signal to turn said second switch element on and off;
and
a second series circuit composed by serial connection of a second current source and a third switch element having a control terminal for receiving the second signal to turn said third switch element on and off;
said first series circuit and said second series circuit being connected in parallel with each other between the node connected to the output terminal and a second power supply;
said bias control unit controlling the bias of the first current source and second current source of said waveform synthesis unit and including:
means for generating a first current and a second current, which exhibit a current-value ratio that conforms to the interior division ratio, in response to two sets of current-path switches being turned on and off based upon the control signal;
and
means for performing control in such a manner that currents corresponding to current values of respective ones of the first current and second current flow into respective ones of the first current source and second current source of said waveform synthesis unit.

8 more elements

An interpolating circuit, having first and second input terminals for receiving first and second signals respectively, for generating and delivering from an output terminal, an output signal having a phase corresponding to a value obtained by dividing a phase difference between the first and second signals in accordance with a interior division ratio set by a control signal supplied from a control signal input terminal, said interpolating circuit comprising a waveform synthesis unit and a bias control unit;

said waveform synthesis unit including:
a logic circuit, receiving the first and second signals, for outputting a result as an output signal of a predetermined logic operation applied to the first and second signals;
a first transistor, inserted between a node connected to the output terminal and a first power supply, having a control terminal for receiving an output signal from said logic circuit to turn said first transistor on and off;
a first series circuit composed by serial connection of a first current source transistor and a second transistor having a control terminal for receiving the first signal to turn said second transistor on and off;
and
a second series circuit composed by serial connection of a second current source transistor and a third transistor having a control terminal for receiving the second signal to turn the third transistor on and off;
said first series circuit and said second series circuit being connected in parallel with each other between the node and a second power supply;
said bias control unit performing control, based upon a control signal that decides the interior division ratio, in such a manner that currents having current values conforming to the interior division ratio will flow into respective ones of the first and second current sources of said waveform synthesis unit;
said bias control unit having a plural sets of circuits each comprising a constant-current source transistor connected to the first power supply, a first switch transistor, inserted between said constant-current source transistor and a first node connected to the control terminal of said first constant-current source transistor, having a control terminal for receiving the control signal that decides the interior division ratio to turn said first switch transistor on and off, and a second switch transistor, inserted between said constant-current source transistor and a second node connected to the control terminal of said second constant-current source transistor, having a control terminal for receiving an inverted signal of the control signal that decides the interior division ratio to turn said second switch transistor on and off;
wherein connection points between the group of first switch transistors and said first node of said plural sets of circuits is connected to a diode-connected fourth transistor, and a control terminal of said diode-connected fourth transistor is connected in common to the control terminal of said first constant-current source transistor;
and
connection points between the group of second switch transistors and second node of said plural sets of circuits are connected to a diode-connected fifth transistor, and a control terminal of said diode-connected fifth transistor is connected in common to the control terminal of the second constant-current source transistor.

9 more elements

Dependencies are inferred from the claim text.

Interpolating circuit, DLL circuit and semiconductor integrated circuit

Life of this patent

Interpolating circuit, DLL circuit and semiconductor integrated circuit

Life of this patent

Abstract

Claims22