Output buffer circuit

An output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting a distributed parameter circuit, comprising:

• (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to said transmission line, and drives said transmission line;
• and
• (b) a second buffer which receives a second logic signal having a predetermined logical relation with said first logic signal, and cooperates with said first buffer to drive said transmission line,
• wherein said second buffer has an output impedance higher than an output impedance of said first buffer,
• said first buffer is comprised of (a1) a first p-channel field effect transistor having a current path between a higher voltage source of two voltage sources and an output terminal, and having a gate electrode electrically connected to a first input terminal, and (a2) a first n-channel field effect transistor having a current path between a lower voltage source of said two voltage sources and said output terminal, and having a gate electrode electrically connected to said first input terminal,
• said second buffer is comprised of a tri-state type buffer including (b1) a second p-channel field effect transistor having a current path between said higher voltage source and said output terminal, and having a gate electrode electrically connected to a second input terminal, (b2) a second n-channel field effect transistor having a current path between said lower voltage source and said output terminal, and having a gate electrode electrically connected to said second input terminal, (b3) a third p-channel field effect transistor electrically connected in series with said second p-channel field effect transistor, and turned on or off in accordance with whether a pre-emphasis step is to be carried out or not, and (b4) a third n-channel field effect transistor electrically connected in series with said second n-channel field effect transistor, and turned on or off simultaneously with said third p-channel field effect transistor,
• said first p-channel field effect transistor having a driving capacity higher than a sum of driving capacities of said second and third n-channel field effect transistors, and
• said first n-channel field effect transistor having a driving capacity higher than a sum of driving capacities of said second and third p-channel field effect transistors.

An output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, comprising:

• (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to said transmission line, and drives said transmission line;
• and
• (b) a second buffer which receives a second logic signal having a predetermined logical relation with said first logic signal, and cooperates with said first buffer to drive said transmission line,
• wherein said second buffer has an output impedance higher than an output impedance of said first buffer,
• said first buffer is comprised of (a1) a first p-channel field effect transistor having a current path between a higher voltage source of two voltage sources and an output terminal, and having a gate electrode electrically connected to a first input terminal, and (a2) a first n-channel field effect transistor having a current path between a lower voltage source of said two voltage sources and said output terminal, and having a gate electrode electrically connected to said first input terminal,
• said second buffer is comprises of first to N-th tri-state type buffers each including (b1) a second p-channel field effect transistor having a current path between said higher voltage source and said output terminal, and having a gate electrode electrically connected to a second input terminal, (b2) a second n-channel field effect transistor having a current path between said lower voltage source and said output terminal, and having a gate electrode electrically connected to said second input terminal, (b3) a third p-channel field effect transistor electrically connected in series with said second p-channel field effect transistor, and turned on or off in accordance with whether a pre-emphasis step is to be carried out or not, and (b4) a third n-channel field effect transistor electrically connected in series with said second n-channel field effect transistor, and turned on or off simultaneously with said third p-channel field effect transistor, wherein N is an integer equal to or greater than 2,
• said first p-channel field effect transistor has a driving capacity higher than a sum of driving capacities of said second and third n-channel field effect transistors in said first to N-th tri-state type buffers, and
• said first n-channel field effect transistor has a driving capacity higher than a sum of driving capacities of said second and third p-channel field effect transistors in said first to N-th tri-state type buffers.