Multiport arbitration using phased locking arbiters
AssigneeCypress Semiconductor Corporation
InventorGrahame K. Reynolds
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Abstract
An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.
Claims18
An apparatus comprising:
- a first arbiter cell configured to lock if one or more requests are not resolved within a first predetermined time period;
- a second arbiter cell configured to dominate if the first arbiter cell enters a metastable state;
- and
- a selection device configured to provide arbitration between said first and second arbiter cells within a second predetermined time period.
An apparatus comprising:
- means for locking if one or more requests are not resolved within a first predetermined time period;
- means for dominating if a metastable state is entered;
- and
- means for arbitrating within a second predetermined time period.
A method for providing arbitration of a plurality of requests for a memory, comprising the steps of:
- (A) locking if one or more requests are not resolved within a first predetermined time period;
- (B) dominating if step (A) enters a metastable state;
- and
- (C) arbitrating between steps (A) and (B) within a second predetermined time period.
Dependencies are inferred from the claim text.