Method and system of evaluating PLL built-in circuit

A method of evaluating a semiconductor device including a PLL circuit, comprising:

• providing a test pattern signal from a test equipment, the test signal being synchronized with a system clock signal received by the test equipment;
• dividing the test signal into M/N frequencies by a frequency divider, wherein M and N are positive integers;
• inputting the divided test signal into the PLL circuit, the PLL circuit outputting an output pattern signal;
• inputting the output pattern signal into the test equipment;
• and
• caring the output pattern signal with the test signal so as to evaluate the semiconductor device, wherein M and N are set in a manner that a frequency of the output pattern signal is substantially equal to a frequency of the system clock signal.

An evaluation system comprising:

• a test equipment for generating a test pattern signal synchronized with a system clock signal received thereto;
• a frequency divider coupled to the test equipment, the frequency divider dividing the test pattern signal received thereto with M/N frequencies and outputting the divided test signal;
• and
• a PLL circuit coupled to the frequency divider for receiving the divided test signal and outputting an output pattern signal having a frequency being N times a frequency of the signal received thereto,
• wherein the test equipment cares the output pattern signal with the test signal so as to evaluate the PLL circuit.