Ball grid array chip packages having improved testing and stacking characteristics

An assembly comprising:

• a board having a first surface and a second surface, the board including at least one electrical circuit for electrical contact with at least one ball grid array of a semiconductor package;
• at least one of the first surface and the second surface of the board comprising:
• a first ball grid array semiconductor package attached to the at least one of the first and second surfaces of the board by a plurality of mutually complementary connective elements connected to the at least one electrical circuit of the board, the first ball grid array semiconductor package comprising:
• a substrate having a first surface, a second surface, and an aperture extending therethrough, a plurality of substrate bond pads located on the first surface adjacent the aperture, and a plurality of mutually discrete conductive circuit traces, each circuit trace of the plurality of circuit traces for extending from at least one of the plurality of substrate bond pads;
• the plurality of mutually complementary connective elements connected to the board being attached to and extending from the second surface of the substrate and arranged in a preselected grid array pattern having at least one preselected pitch dimension between adjacent connective elements, each connective element connected to a circuit trace of the plurality of circuit traces;
• a semiconductor device having an active surface and a plurality of bond pads located thereon, the semiconductor device attached to the second surface of the substrate and positioned adjacent to the board;
• and
• a plurality of bond wires extending through the aperture, each of the plurality of bond wires connecting one of the plurality of bond pads on the active surface of the semiconductor device with one of the plurality of substrate bond pads on the first surface of the substrate.