Single and multilevel rework

An integrated circuit structure comprising:

• a section comprising logical and functional devices;
• and
• a plurality of interconnection layers above said section, wherein each of said interconnection layers comprises:
• a first insulator layer;
• a second insulator layer above said first insulator layer;
• and
• an electrical wiring within said first insulator layer and said second insulator layer,
• wherein said first insulator layer has a lower dielectric constant than that of said second insulator layer,
• wherein an upper interconnection layer above a lower interconnection layer of said interconnection layers comprises a reworked interconnection layer having larger vias when compared to corresponding vias in said lower interconnection layer, and
• wherein size differences between said corresponding vias in said reworked interconnection layer and vias in said lower interconnection layer compensate for pitch inconsistencies between original fabrication and rework.

An integrated circuit structure comprising:

• a section comprising logical and functional devices;
• and
• a plurality of interconnection layers above said section, wherein each of said interconnection layers comprises:
• a first insulator layer;
• a second insulator layer above said first insulator layer;
• and
• an electrical wiring within said first insulator layer and said second insulator layer,
• wherein said first insulator layer has a lower dielectric constant than that of said second insulator layer,
• wherein an upper interconnection layer above a lower interconnection layer of said interconnection layers comprises a reworked interconnection layer having vias approximately 30% larger than corresponding vias in said lower interconnection layer, and
• wherein size differences between said corresponding vias in said reworked interconnection layer and vias in said lower interconnection layer compensate for pitch inconsistencies between original fabrication and rework.