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US 6,674,157 B2Granted
Semiconductor package comprising vertical power transistor
AssigneeFairchild Semiconductor Corporation
InventorDennis Lang
Life of this patent
Estimating the term…
Abstract
A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die having a vertical power transistor, a first surface and a second surface. A ground plane proximate the second surface and distal to the first surface. A bus member covers a portion the first surface of the semiconductor die and has at least one leg that electrically couples a source region of the semiconductor die to the ground plane.
Claims19
A semiconductor die package comprising:
- a semiconductor die comprising a vertical power transistor, wherein the semiconductor die has a first Surface and a second surface;
- a source region at the first surface of the semiconductor die;
- a gate at to first surface of the semiconductor die;
- a drain region at the second surface of the semiconductor die;
- a ground plane proximate the second surface and distal to the first surface;
- and
- a bus member covering a portion of the flit surface of the semiconductor die and having at least one leg, wherein the bus member electrically couples the Source region of the semiconductor die to the ground plane.
4 more elements
A semiconductor die package comprising:
- a semiconductor die comprising a vertical power transistor, wherein the semiconductor die has a first surface and a second surface;
- a source region at the first surface of the semiconductor die;
- a gate at the first surface of the semiconductor die;
- a drain region at the second surface of the semiconductor die;
- a ground plane proximate the second surface and distal to the first surface;
- a conductive layer between the ground plant and the semiconductor die;
- an isolator layer disposed between the conductive layer and the ground plane;
- a bus member covering a major portion of the first surface of the semiconductor die and electrically coupling the source region of the semiconductor die to the ground plane;
- a carrier enclosing the semiconductor die and the bus member;
- a drain lead passing through the carrier;
- a first electrical conductor coupling the drain lead to the conductive layer and the drain region;
- a gate lead passing through the carrier;
- and
- a second electrical conductor coupling the gate lead to the gate.
11 more elements
A semiconductor die package comprising:
- a semiconductor die comprising a vertical power transistor, wherein the semiconductor die has a first surface and a second surface;
- an emitter region at the first surface of the semiconductor die;
- a base region at the first surface of the semiconductor die;
- a collector region at the second surface of the semiconductor die;
- a ground plane proximate the second surface and distal to the first surface;
- and
- a bus member covering a portion of the first surface of the semiconductor die and having at least one leg, wherein the bus member electrically coup lea the emitter region of the semiconductor die to the ground plane.
4 more elements
A semiconductor die package comprising:
- a semiconductor die comprising a transistor, wherein the semiconductor die has a first suffice and a second surface;
- a source region in the semiconductor die;
- a gate in the semiconductor die;
- a drain region in the semiconductor die;
- a ground plane proximate the second surface and distal to the first surface;
- and
- a bus member covering a portion of the first surface of the semiconductor die and having at least one leg, wherein the bus member electrically couples the source region of the semiconductor die to the ground plane.
4 more elements
Dependencies are inferred from the claim text.