Use of high-k dielectric materials in modified ONO structure for semiconductor devices
AssigneeAdvanced Micro Devices, Inc.
InventorsArvind Halliyal, Mark T. Ramsbey, Kuo-Tung Chang, Nicholas H. Tripsas, Robert B. Ogle
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Abstract
A process for fabrication of a semiconductor device including a modified ONO structure, including forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.
Claims16
A semiconductor device comprising a modified ONO structure, wherein the modified ONO structure comprises
- a bottom oxide layer;
- a layer comprising a composite dielectric material on the bottom oxide layer, wherein the composite dielectric material comprises elements of at least one high-K dielectric material;
- and
- a top oxide layer on the layer comprising a composite dielectric material.
A non-volatile memory cell comprising:
- a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween;
- b) a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric film;
- and
- c) a control gate positioned above the floating gate and separated from the floating gate by an interpoly dielectric layer, the interpoly dielectric layer comprising a bottom silicon dioxide layer adjacent to the floating gate, a top silicon dioxide layer adjacent to the control gate, and a center layer comprising a high-K dielectric material and positioned between the bottom silicon dioxide layer and the top silicon dioxide layer, with the proviso that when the center layer comprises tantalum oxide (Ta2O3), the center layer further comprises at least one additional dielectric material.
A non-volatile memory cell comprising:
- a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween;
- b) a charge storage layer comprising a modified ONO structure, having a bottom silicon dioxide layer adjacent the channel region, a top silicon dioxide layer, and a center charge storage layer comprising a high-K dielectric material and positioned between the bottom silicon oxide layer and the top silicon dioxide layer;
- and
- c) a gate capacitively coupled to the channel region through the charge storage layer.
A non-volatile memory cell comprising:
- a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween;
- b) a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric film;
- and
- c) a control gate positioned above the floating gate and separated from the floating gate by an interpoly dielectric layer, the interpoly dielectric layer comprising a single layer adjacent to both the floating gate and the control gate, the single layer comprising a dielectric material, wherein the dielectric material is a metal silicate, a metal aluminate or a metal mixed-aluminate-silicate.
Dependencies are inferred from the claim text.