Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric
AssigneeAdvanced Micro Devices, Inc.
InventorsJon Cheek, Derick Wristers, Mark I. Gardner
Life of this patent
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Abstract
A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions. The metal gate electrode is aligned using a polysilicon alignment structure, which permits high temperature processing before the metal is deposited.
Claims19
A semiconductor structure, comprising:
- a substrate;
- a first gate dielectric layer formed on the substrate between nitride spacers;
- a second gate dielectric layer formed on the first gate dielectric layer;
- a metal gate electrode formed on the second gate dielectric layer;
- a pair of lightly-doped drain regions in the substrate adjacent to the spacers, wherein at least a portion of each of the lightly-doped drain regions is directly below the gate electrode;
- a pair of source/drain regions in the substrate adjacent to the spacers, wherein each of the source/drain regions is aligned with a respective one of the spacers;
- an epitaxial layer disposed on the substrate adjacent to the spacers;
- and
- a silicide layer disposed on the epitaxial layers.
A semiconductor structure comprising:
- a substrate;
- a first gate dielectric formed on the substrate;
- a second gate dielectric formed on the first gate dielectric, separate from the first gate dielectric, and having a width about equal to the first gate dielectric;
- a metal gate electrode formed on the second gate dielectric layer and having a width about equal to the first and second gate dielectrics;
- nitride spacers formed on the substrate and adjacent each of the first and second gate dielectrics and the metal gate electrode;
- a pair of lightly-doped drain regions in the substrate adjacent to and below the spacers, wherein at least a portion of each of the lightly-doped drain regions is directly below the gate electrode;
- a pair of source/drain regions in the substrate adjacent to the spacers, wherein each of the source/drain regions is aligned with a respective one of the spacers and extend from a side of the spacer and horizontally away from the gate dielectrics and electrode, the source/drain regions being formed below a plane including an interface between the first gate dielectric and the substrate;
- epitaxial layers disposed on the substrate, adjacent each of the spacers and extending away from the gate dielectrics and electrode;
- and
- a silicide layer disposed on the epitaxial layers.
A semiconductor structure having a gate structure formed on a substrate, the gate structure comprising:
- a first gate dielectric formed on the substrate;
- a second gate dielectric formed on the first gate dielectric, separate from the first gate dielectric, and having a width about equal to the first gate dielectric;
- a metal gate electrode formed on the second gate dielectric layer and having a width about equal to the first and second gate dielectrics;
- and
- nitride spacers formed on the substrate and adjacent each of the first and second gate dielectrics and the metal gate electrode.
Dependencies are inferred from the claim text.