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AssigneeInternational Business Machines Corporation
InventorsWayne S. Berry, Jeffrey P. Gambino, Jack A. Mandelman, William R. Tonti
Estimating the term…
The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.
An integrated circuit comprising:
An I/O device comprising a plurality of nested narrow mesa MOSFET device regions and a plurality of wider mesa MOSFET device regions, each adjacent nested narrow mesa MOSFET device region and each adjacent wider mesa MOSFET device region is located in raised portions of a semiconductor substrate and is separated by a shallow trench isolation region, wherein each of said nested narrow mesa MOSFET device regions has a gate oxide that is thicker than a corresponding gate oxide of said wider mesa MOSFET device region, said gate oxide of each of said nested narrow mesa MOSFET device regions having a thickness of from about 5 to about 14 nm and said gate oxide of each of said wider mesa MOSFET device regions having a thickness of from about 2.5 to about 4 nm.
Dependencies are inferred from the claim text.