High performance PD SOI tunneling-biased MOSFET

A tunneling-biased PMOSFET structure comprising:

• an N-type silicon body having a top surface and a buried oxide layer located a distance below said top surface;
• oxide filled trenches that extend downwards from said top surface as far as said buried layer, said trenches being disposed so as to fully enclose a volume of N-type silicon, thereby forming an N-well;
• a polysilicon gate pedestal, having two opposing long sides that extend from a first end over a first oxide filled trench across said N-well to a second end abutting a second oxide filled trench;
• between said gate pedestal and said upper surface, with no intervening layers, a dielectric layer having a thickness that is less than the tunneling threshold of said dielectric layer;
• a P-type region within said N-well that abuts both of said long sides and that does not overlap either of said ends, said P-type region constituting source and drain areas disposed on opposing sides of said gate pedestal;
• and
• an N+ region within said polysilicon gate, extending inwards from one of said ends, said N+ region constituting a tunneling connection between said N-well and said polysilicon gate.