Semiconductor integrated circuit device
AssigneeHitachi, Ltd.
InventorsYoshitaka Tadaki, Yutaka Ito
Life of this patent
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Abstract
A semiconductor integrated circuit device has a semiconductor substrate and operates when supplied with appositive supply voltage and a circuit ground potential. The device has word lines, pairs of bit lines, data storage capacitors, and N-channel MOSFETs each having a gate connected to any one of the word lines and a source-drain path interposed between one of the paired bit lines on the one hand and a terminal of any one of the data storage capacitors on the other hand. A positive internal voltage higher than a circuit ground potential is generated and fed as a bias voltage to P-type regions wherein address selection MOSFETs of dynamic memory cells are formed.
Claims27
A semiconductor integrated circuit device comprising:
- dynamic memory cells made of N-channel address selection MOSFETs each having a gate, a source and a drain, said gate being connected to a word line, either of said source and said drain being connected to bit lines intersecting said word line, the other of said source and said drain being connected to a storage node of a data storage capacitor;
- a peripheral circuit which performs select, write and read operations on any of said dynamic memory cells;
- a P-type well region in which said address selection MOSFETs are formed;
- and
- an internal power supply circuit which supplies said P-type well region with a positive bias voltage higher than a circuit ground potential.
A semiconductor integrated circuit device having a memory portion including a dynamic RAM comprising:
- dynamic memory cells made of N-channel address selection MOSFETs each having a gate, a source and a drain, said gate being connected to a word line, either of said source and said drain being connected to bit lines intersecting said word line, the other of said source and said drain being connected to a storage node of a data storage capacitor;
- a peripheral circuit which performs select, write and read operations on any of said dynamic memory cells;
- a P-type well region in which said address selection MOSFETs are formed;
- and
- an internal power supply circuit which supplies said P-type well region with a positive bias voltage higher than a circuit ground potential;
- said semiconductor integrated circuit device further comprising a logic control circuit portion for inputting and outputting data at least to and from said memory portion.
A semiconductor integrated circuit device having a semiconductor substrate and operating when supplied with a positive supply voltage and a circuit ground potential, said semiconductor integrated circuit device comprising:
- word lines;
- pairs of bit lines;
- data storage capacitors;
- N-channel MOSFETs each having a gate connected to any one of said word lines and a source-drain path interposed between one of the paired bit lines on the one hand and a terminal of any one of said data storage capacitors on the other hand;
- and
- a circuit for generating a positive internal voltage which is higher than said circuit ground potential;
- wherein source and drain regions constituting said N-channel MOSFETs are formed in P-type region of said semiconductor substrate;
- and
- wherein said positive internal voltage is supplied to said P-type region.
Dependencies are inferred from the claim text.