Single transistor ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric

An integrated circuit device formed on a single substrate including a memory array having a plurality of memory cells coupled to at least one word line, plate line and bit line of said memory array, at least one of said memory cells comprising:

• a 1T transistor having a ferroelectric dielectric formed intermediate of said substrate and a control terminal thereof coupled to said word line, said transistor further comprising first and second terminals coupled respectively to said bit line and plate line;
• an interfacial layer in contact with said ferroelectric dielectric interposed between said ferroelectric dielectric and said substrate;
• and
• wherein said interfacial layer is an oxide of a material selected from a group comprising A=Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu or Sc having the general formula AxSiyOz, where x,y are values between about 0.1 and 10.