Process for forming MOS-gated power device having segmented trench and extended doping zone

A process for forming a trench MOS-gated device, said process comprising:

• providing a substrate having an upper surface and comprising doped monocrystalline semiconductor material of a first conduction type;
• forming a trench in an upper layer of said substrate, said trench having a floor and sidewalls, said trench further having a width and extending to a depth substantially corresponding to a width and a depth of the upper segment of an extended trench comprising an upper segment and a bottom segment;
• forming a conformal masking oxide layer on said substrate upper layer and on said trench floor and sidewalls;
• anisotropically etching said conformal masking oxide layer, thereby removing said masking oxide from said trench floor and forming an opening to substrate semiconductor material underlying said floor;
• etching said semiconductor material underlying said trench floor, thereby forming said bottom segment of said extended trench, said bottom segment having a lesser width relative to a greater width of said trench upper segment and extending to a depth corresponding to the total depth of said extended trench;
• removing remainder of conformal masking oxide layer from said substrate upper layer and from said trench sidewalls;
• substantially filling said extended trench with a dielectric material;
• selectively implanting and diffusing a dopant of a second opposite conduction type into said upper layer on one side of said extended trench, thereby forming an extended zone extending from said substrate upper surface into said upper layer;
• selectively removing said dielectric material from said upper segment of said extended trench, leaving said bottom segment of said extended trench substantially filled with said dielectric material;
• forming floor and sidewalls comprising dielectric material in said upper segment of said extended trench and substantially filling said upper segment with a conductive material, thereby forming a gate region in said upper segment of said extended trench;
• forming a doped well region of said second conduction type in said upper layer on the side of said extended trench opposite said extended zone;
• forming a heavily doped source region of said first conduction type and a heavily doped body region of said second conduction type in said well region at said upper surface;
• forming an interlevel dielectric layer on said upper surface overlying said gate and source regions;
• and
• forming a metal layer overlying said upper surface and said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions and said extended zone.