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US 6,673,665 B2Granted
Semiconductor device having increased metal silicide portions and method of forming the semiconductor
AssigneeAdvanced Micro Devices, Inc.
InventorsKarsten Wieczorek, Manfred Horstmann, Rolf Stephan
Life of this patent
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Abstract
The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed so as to react with a refractory metal to form a low resistance silicide. The upper portion may be exposed by overetching the dielectric layer deposited to form the sidewall spacers.
Claims24
A method, comprising:
- forming a conductive silicon-containing feature, said feature having sidewalls and an upper surface;
- forming spacer elements adjacent to a portion of said sidewalls, said spacer elements covering less than all of said sidewalls and defining an exposed portion of said sidewalls by depositing a layer of a dielectric material on the upper surface and upper and lower sidewall portions of the conductive silicon-containing feature, with the layer of dielectric material being thicker at the lower sidewall portions of the conductive silicon-containing feature than on the upper surface portion of the conductive silicon-containing feature and isotropically etching the dielectric material by performing a single isotropic etching process until the upper sidewall portion is exposed;
- forming a metal layer on at least the upper surface and exposed portion of the sidewalls;
- and
- forming a metal silicide on said upper surface and said exposed portion of said sidewalls by performing at least one thermal treatment.
2 more elements
A method of forming the gate electrode of at least one field effect transistor to be formed on a substrate, the method comprising:
- forming at least one line of polysilicon on an active region of the at least one transistor;
- forming dielectric sidewall spacers on the lower portion of the sidewalls of the at least one polysilicon line by depositing a layer of a dielectric material on the upper surface and the upper and lower sidewall portions of the at least one polysilicon line, with the layer of dielectric material being thicker at the lower sidewall portions of the at least one polysilicon line than on the upper surface portion of the polysilicon line;
- performing a single isotropic etching process to isotropically etch the dielectric material to expose the upper surface and the upper sidewall portions of the at least one polysilicon line;
- forming a metal layer on the upper surface and the exposed upper portions of the sidewalls of the at least one polysilicon line;
- and
- reacting at least partially the polysilicon and the metal at the polysilicon metal interface into metal silicide by a thermal treatment.
3 more elements
Dependencies are inferred from the claim text.