Self-aligned method for forming dual gate thin film transistor (TFT) device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi-Wen Liu, Ting-Chang Chang, Po-Tsun Liu, Ying-Lang Wang
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Abstract
A method for fabricating a dual gate thin film transistor (TFT) device provides for forming a pair of source/drain layers self-aligned with respect to a first gate electrode and forming a second gate electrode self-aligned with respect to both the pair of source/drain layers and the first gate electrode. Thus, the dual gate TFT device is fabricated with enhanced alignment. In addition, the dual gate TFT device (or a single gate TFT device) may be fabricated with source/drain layers formed of a silicon-germanium alloy material, such as to provide the TFT device with enhanced performance with respect to a kink effect.
Claims13
A method for fabricating a thin film transistor comprising:
- providing a planar substrate;
- forming over the planar substrate a topographic first gate electrode;
- forming upon the topographic first gate electrode a first gate dielectric layer;
- forming separated by the first gate electrode and the first gate dielectric layer a pair of source/drain layers;
- forming upon the pair of source/drain layers and the first gate dielectric layer a semiconductor channel layer which forms a recess with respect to the pair of source/drain layers;
- forming upon the semiconductor channel layer a second gate dielectric layer;
- and
- forming upon the second gate dielectric layer and also separating the pair of source/drain layers a second gate electrode, wherein:
- the pair of source/drain layers is formed in a self-aligned fashion with respect to the first gate electrode;
- and
- the second gate electrode is formed in a self-aligned fashion with respect to the pair of source/drain layers and the first gate electrode.
A method for fabricating a thin film transistor comprising:
- providing a planar substrate;
- forming over the planar substrate a topographic first gate electrode;
- forming conformally upon the topographic first gate electrode a first gate dielectric layer;
- forming conformally upon the first gate dielectric layer a planarizing stop layer;
- forming upon the planarizing stop layer a silicon-germanium alloy material layer;
- planarizing the silicon-germanium alloy material layer to reach the planarizing stop layer and form a pair of source/drain layers separated by the topographic first gate electrode;
- stripping from over the first gate dielectric layer a portion of the planarizing stop layer to expose a portion of the first gate dielectric layer;
- forming conformally upon exposed portions of the pair of source/drain layers and the first gate dielectric layer a semiconductor channel layer which forms a recess with respect to the pair of source/drain layers;
- forming conformally upon the semiconductor channel layer a second gate dielectric layer;
- forming upon the second gate dielectric layer a second gate electrode material layer;
- and
- planarizing the second gate electrode material layer to form a second gate electrode within the recess defined by the pair of source/drain layers.
Dependencies are inferred from the claim text.