Delay estimation for restructuring
AssigneeCadence Design Systems, Inc.
InventorsJohnson Chan Limqueco, Hong Li, Krishna Belkhale, Devadas Varma
Life of this patent
Estimating the term…
Abstract
Provided are a method, article of manufacture, and apparatus for estimating delays of networks. An automated design system comprises a computer configured to identify a critical path in a network, calculate a delay for the technology-mapped version of the network, calculate a delay for the technology-independent version of the network, calculate a scale factor from the technology-mapped and technology-independent delays, and apply the scale factor to all the delays in the technology-independent network.
Claims48
A method of estimating delays in a circuit, comprising the steps of:
- selecting a first path in the circuit;
- calculating a technology-mapped delay for the first path;
- calculating a technology-independent delay for the first path;
- dynamically calculating a scale factor from the technology-mapped delay and the technology-independent delay, wherein the step of calculating the scale factor includes dividing the technology-mapped delay by the technology independent delay;
- and
- applying the scale factor to at least one delay in the circuit, wherein the step of applying the scale factor includes multiplying the at least one delay by the scale factor.
A method of optimizing a circuit, comprising the steps of:
- producing a technology-mapped form of the circuit;
- identifying a technology-mapped critical path in the technology-mapped circuit;
- producing a technology-independent form of the circuit;
- dynamically calculating a scale factor, wherein the step of calculating the scale factor includes dividing the technology-mapped delay by the technology independent delay;
- applying the scale factor to the technology-independent circuit, wherein the step of applying the scale factor includes multiplying the at least one delay by the scale factor;
- and
- restructuring the technology-independent circuit.
A computer program product for estimating delays in a circuit, comprising a computer usable medium having a machine readable code embodied therein for performing the steps of:
- selecting a first path in the circuit;
- calculating a technology-mapped delay for the first path;
- calculating a technology-independent delay for the first path;
- dynamically calculating a scale factor from the technology-mapped delay and the technology-independent delay, wherein the step of calculating the scale factor includes dividing the technology-mapped delay by the technology independent delay;
- and
- applying the scale factor to at least one delay circuit, wherein the step of applying the scale factor includes multiplying the at least one delay by the scale factor.
An automated design system for estimating delays in a circuit, comprising:
- a processor;
- and
- a memory in communication with the processor;
- wherein the processor is configured to select a first path in the circuit, calculate a technology-mapped delay for the first path, calculate a technology-independent delay for the first path, dynamically calculate a scale factor from the technology-mapped delay and the technology-independent delay, wherein the step of calculating the scale factor includes dividing the technology-mapped delay by the technology independent delay, and apply the scale factor to at least one delay in the circuit, wherein the step of applying the scale factor includes multiplying the at least one delay by the scale factor.
Dependencies are inferred from the claim text.