Multi-layer circuit assembly and process for preparing the same

A process for fabricating a multi-layer circuit assembly comprising the following steps:

• (a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter);
• (b) applying a dielectric coating onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core;
• (c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core;
• (d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core;
• (e) applying a resinous photosensitive layer to the metal layer;
• (f) placing a photo-mask having a desired pattern over the photosensitive layer to form a layered substrate with selected exposed portions;
• (g) exposing the layered substrate to a suitable actinic radiation source;
• (h) removing the photo-mask and developing the layered substrate to remove more soluble portions of the photosensitive layer from the underlying metal layer and to uncover selected areas of the metal layer;
• (i) etching any uncovered metal to remove it from the underlying dielectric coating;
• and
• (j) stripping the remaining resinous photosensitive layer to provide a circuit pattern connected by the metallized vias.