Processor including a translation unit for selectively translating virtual addresses of different sizes using a plurality of paging tables and mapping mechanisms

A processor comprising:

• an execution core configured to generate a virtual address;
• and
• a translation unit configured to translate the virtual address to a physical address using:
• if a first operating mode is selected, either a first or a second plurality of paging tables, wherein each of the paging tables in the first plurality comprises a plurality of entries that each have a first entry size, wherein each of the paging tables in the second plurality comprises a plurality of entries that each have a second entry size, wherein the second entry size is greater than the first entry size, and wherein the first plurality of paging tables and the second plurality of paging tables are each configured to support virtual addresses having at most a first number of bits;
• and
• if a second operating mode is selected, a third plurality of paging tables, wherein each of the paging tables in the third plurality comprises a plurality of entries that have the second entry size, wherein there are more levels of paging tables in the third plurality of paging tables than in the second plurality of paging tables, and wherein the third plurality of paging tables is configured to support virtual addresses having more than the first number of bits;
• wherein the translation unit is configured to translate the virtual address to the physical address using the third page mapping mechanism both when a first virtual address size having more than the first number of bits is selected and when a second virtual address size having at most the first number of bits is selected.