Synchronous semiconductor allowing replacement with redundant memory cell while maintaining access time
AssigneesMitsubishi Denki Kabushiki Kaisha, Texas Instruments Incorporated
InventorsTsukasa Ooishi, Hiroya Nakamura
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Abstract
The higher order bit of the output from an address latch circuit is applied to a predecoder that operates a predecode signal to select a column select line and to a redundancy decoder to select a redundant column. The lower order bit of the address signal is generated by a burst address counter and applied to the predecoder. A comparison result for the higher order bit is calculated in advance at the redundancy decoder. When the lower order bit is applied to the redundancy decoder and the calculation of the comparison result ends, the redundancy determination is output from a redundancy determination unit.
Claims12
A synchronous semiconductor memory device receiving an address signal including a plurality of bits synchronized with an external clock signal comprising:
- a memory cell array including a plurality of memory cells arranged in a matrix, said memory cell array including
- a regular memory cell block, and
- a redundant memory cell block corresponding to said regular memory cell block for replacing a defective memory cell in a corresponding regular memory cell block;
- and
- a memory cell select circuit selecting a regular memory cell in said regular memory cell block or a redundant memory cell in said redundant memory cell block in response to the address signal, said memory cell select circuit including a redundancy determination circuit to determine whether to replace a defective memory cell with said redundant memory cell by dividing the address signal into a plurality of signal groups and comparing each signal group with a defective bit address for each signal group.
A synchronous semiconductor memory device receiving an address signal including a plurality of bits synchronized with an external clock signal, comprising:
- a clock signal generating an internal clock signal in response to the external clock signal;
- a memory cell array including a plurality of memory cells arranged in a matrix, said memory cell array including
- a regular memory cell block, and
- a redundant memory cell block corresponding to said regular memory cell block for replacing a defective memory cell in a corresponding regular memory cell block;
- and
- a memory cell select circuit selecting a regular memory cell in said regular memory cell block or a redundant memory cell in said redundant memory cell block in response to the address signal, said memory cell select circuit including a redundancy determination circuit to determine whether to replace a defective memory cell with said redundant memory cell by dividing the address signal into a plurality of signal groups and comparing each signal group with a defective bit address for each signal group, said memory cell select circuit carrying out a select operation in response to a determination result of said redundancy determination circuit delayed for n internal clock signal cycles, in synchronization with the internal clock signal, wherein n is a natural number.
Dependencies are inferred from the claim text.