Microengine for parallel processor architecture
AssigneeIntel Corporation
InventorsDebra Bernstein, Donald F. Hooper, Matthew J. Adiletta, Gilbert Wolrich, William Wheeler
Life of this patent
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Abstract
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
Claims41
A microcontrolled functional execution unit comprises:
- a control store to store a microprogram;
- a microengine controller for maintaining a plurality of microprogram counters, and decode logic for decoding instructions;
- a context event arbiter, which in response to external flags, determines which one of a plurality of threads executable in the microcontrolled functional execution unit to promote to an execution state.
A network processor, comprising:
- at least one shared resource;
- and
- a collection of microcontrolled functional execution units communicatively coupled to the at least one shared resource, individual ones of the execution units to switch contexts between different threads executable in the execution unit, the threads to issue requests for operations on the at least one shared resource, the individual execution units including a context event arbiter to determine which one of the threads to execute based, at least in part, on signals indicating when a thread's requested operation on the at least one shared resource completes.
A method comprising:
- in a network processor, switching contexts between different threads executing in microcontrolled functional execution units, the threads issuing requests for operations on at least one shared resource, each of the execution units including a context event arbiter to determine which one of the threads to execute based, at least in part, on signals indicating when a thread's requested operation on a shared resource completes.
Dependencies are inferred from the claim text.