Self-repair of embedded memory arrays

An embedded memory unit, comprising:

• a memory array having a design size given by an integer n, the array comprising:
• a matrix of memory cells arranged in n+1 lines;
• and
• selection circuitry, coupled to select n of the n+1 lines to which data are to be written and from which the data are to be read;
• a built-in self-test (BIST) circuit, coupled to test the memory array by writing test data to the memory array, reading the data from the memory array, and comparing the data read from the array to the test data written thereto, and adapted to generate a binary output indicating whether or not the data read from the array correspond correctly to the test data written to the array;
• and
• a repair machine, coupled to receive the binary output of the BIST circuit and to drive the selection circuitry to select different sets of n of the lines while driving the BIST circuit to test the memory array, so as to find one of the different sets for which the binary output indicates that the data read from the array correspond correctly to the test data written to the array.