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US 6,667,641 B1Granted
Programmable phase shift circuitry
AssigneeAltera Corporation
InventorsBonnie I. Wang, Joseph Huang, Chiakang Sung, Xiaobao Wang, In Whan Kim, Wayne Yeung, Khai Nguyen
Life of this patent
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Abstract
A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.
Claims27
A programmable logic integrated circuit comprising:
- a programmable interconnect structure including rows of horizontal conductors and columns of vertical conductors;
- a phase detector circuit receiving a reference clock signal;
- a charge pump circuit coupled to the phase detector circuit;
- a voltage controlled oscillator, coupled to the charge pump and programmably coupled to the logic array blocks, wherein the voltage controlled oscillator generates a plurality of voltage controlled oscillator outputs;
- and
- a first multiplexer coupled to the voltage controlled oscillator, wherein the multiplexer selects one of the voltage controlled oscillator outputs as a first clock output,
- wherein the voltage controlled oscillator comprises second, third and fourth multiplexer an input of the second multiplexer coupled to an output of the third multiplexer, an input of the third multiplexer coupled to an output of the fourth multiplexer, and an input of the fourth multiplexer coupled to an output of the third multiplexer.
4 more elements
A programmable logic integrated circuit comprising:
- a programmable interconnect structure;
- a plurality of logic array blocks, configurable to perform logic functions and programmably coupled to the programmable interconnect structure;
- a phase detector circuit receiving a reference clock signal;
- a charge pump circuit coupled to the phase detector circuit;
- a voltage controlled oscillator, coupled to the charge pump and programmably coupled to the logic array blocks, wherein the voltage controlled oscillator generates a plurality of voltage controlled oscillator outputs;
- and
- a first multiplexer coupled to the voltage controlled oscillator, wherein the multiplexer selects one of the voltage controlled oscillator outputs as a first clock output,
- wherein the voltage controlled oscillator comprises;
- a second multiplexer coupled between first and second voltage controlled oscillator outputs, a third multiplexer coupled between the second and a third voltage controlled oscillator outputs, and a fourth multiplexer coupled between the third and a fourth voltage controlled oscillator outputs.
6 more elements
A programmable logic integrated circuit comprising:
- a programmable interconnect structure including rows and columns of interconnect conductors;
- and
- a phase locked loop circuit generating an internal clock signal that is programmably coupled to the logic array blocks, wherein a phase shift between a reference clock signal and the internal clock signal is user selectable,
- wherein the phase locked loop circuit includes a voltage controlled oscillator that comprises first and second multiplexers, the first multiplexer having inputs coupled to first and second voltage controlled oscillator outputs and an output coupled to a third voltage controlled oscillator output the second multiplexer having inputs coupled to the third and a fourth voltage controlled oscillator outputs and an output coupled to the first voltage controlled oscillator output.
1 more element
A circuit comprising:
- a phase detector circuit receiving a reference clock signal;
- a charge pump circuit coupled to the phase detector circuit;
- a voltage controlled oscillator coupled to the charge pump, wherein the voltage controlled oscillator generates a plurality of voltage controlled oscillator outputs;
- and
- a first multiplexer coupled to the voltage controlled oscillator, wherein the multiplexer selects one of the voltage controlled oscillator outputs as a fist clock output, the first clock output is coupled to the phase detector circuit, one of the plurality of voltage controlled oscillator outputs is a second clock output, and a phase shift between the reference clock signal and the second clock output is programmably selectable by a user,
- wherein the voltage controlled oscillator comprises a second multiplexer and a plurality of delay stages coupled in a loop, a number of the delay stages enabled in the loop being programmable.
3 more elements
A programmable logic integrated circuit comprising:
- a programmable interconnect structure;
- a plurality of logic array blocks, configurable to perform logic functions, and programmably coupled to the programmable interconnect structure;
- and
- a phase locked loop circuit generating an internal clock signal that is programmably coupled to the logic array blocks, wherein a phase shift between a reference clock signal and the internal clock signal is user selectable,
- wherein the phase locked loop circuit includes a voltage controlled oscillator that comprises a first multiplexer having inputs coupled to first and second voltage controlled oscillator outputs, a second multiplexer having inputs coupled to third and fourth voltage controlled oscillator outputs, and a third multiplexer having an input coupled to the first voltage controlled oscillator output.
2 more elements
An integrated circuit comprising:
- a phase locked loop circuit generating an internal clock signal that is programmably coupled to the logic array blocks, wherein a phase shift between a reference clock signal and the internal clock signal is user selectable,
- wherein the phase locked loop circuit includes a voltage controlled oscillator that comprises first, second, and third multiplexers coupled in a loop.
Dependencies are inferred from the claim text.