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US 6,667,522 B2Granted
Silicon wafers for CMOS and other integrated circuits
AssigneeIntel Corporation
InventorsKramadhati V. Ravi, Li Ling, Sing-Chung S. Hu
Life of this patent
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Abstract
Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer and forming at least one electrical circuit element in the near-surface region. Integrated circuits or other devices may include a semiconductor wafer with a substantially uniformly boron-doped bulk region and a reduced boron concentration layer near a surface of the wafer. An electrical circuit element may be provided in the reduced boron concentration layer.
Claims7
An apparatus comprising:
- a silicon semiconductor wafer including:
- a surface;
- a substantially uniformly boron-doped bulk region having a resistivity in a range of about 10 to 1,000 milli-ohm-centimeter;
- and
- a reduced boron concentration layer near the surface, wherein the reduced boron concentration layer extends along the surface and has a boron gradient that increases substantially continuously with increasing depth from the surface to a depth in a range of about 0.1 to 1.0 micron, and wherein the reduced boron concentration layer has a resistivity in a range of about 0.5 to 10 ohm-centimeter;
- and
- an electrical circuit element in the reduced boron concentration layer.
4 more elements
Dependencies are inferred from the claim text.